Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [libero]

Libero is the software for the design of Actel (Microsemi) FPGAs.

22 questions
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5 answers

Why do FPGA projects always take the same amount of time to compile?

With software, when we compile the project for first time it may take a while but afterwards, it does not take so long anymore. If we change a single file in the project, everything does not need to be compiled again. This does not seem to hold true…
gyuunyuu
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4 answers

Is using floor plan tool during FPGA design ever actually useful or required?

I have used Intel Quartus and Microsemi Libero. Both of these tools contain a method whereby we are able to view the floorplan of the FPGA, hover the mouse around to see what parts of netlist have been mapped to different locations on the FPGA…
gyuunyuu
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2 answers

What are the various files types in Actel (Microsemi) Libero?

While researching What files/directories are needed to recreate a Actel/Microsemi Igloo2 project?, I found about various files types. But not all are defined in the Libero SoC or Design Constraints, both v11.2 User's Guides. Specifically what are…
Brian Carlton
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1 answer

Smartfusion2 Programmer Error

I have recently start using the M2S150 Development kit from Microsemi and have run into an issue when attempting to program the board (via Libero 12.1). When running the "Run PROGRAM Action" command the log reports the following Error: programmer…
EpicFoodCartDestroyer
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1 answer

What is the proper methodology to create portable FPGA designs?

FPGA designs may contain RTL along with IP blocks. These IP blocks most likely shall be from the vendor of the FPGA. Examples of such IP blocks are instantiating dual clock FIFOs, floating point and fixed point maths blocks so we can precisely set…
quantum231
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1 answer

Is there a Quartus Signal Tap II equivalent for the Microsemi Libero SoC?

Quartus Signal Tap is extremely beneficial in debugging complex problems. However, there is no such toolset in the Microsemi Libero SmartDebug toolset. I would expect that Microsemi does provide capability to create an internal logic analyzer by…
quantum231
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3 answers

0 definitions of operator "*" match here for signed type (numeric_std, VHDL)

I'm writing a package to add supporting functions and types for creating an FIR filter. In the mult function, I'm trying to multiply two signed types, which should be supported in IEEE.numeric_std library. The error I'm getting (using Libero IDE)…
Prabhpreet
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0 answers

Microsemi Libero tool version shell command

Is there any shell script command for getting the libero tool version ? I want that shell script command. As far as I know, libero tools have get_libero_release command for getting the tool version but this is the tcl command not shell script…
Niranjan Nimgaonkar
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1 answer

How to use "AND" statement in Verilog

I am trying to create a counter that starts counting when a start signal goes from 0 to 1. Then, I want the counter to keep counting until both the start and stop signal are 1. Once both signals are 1 the counter should reset to 0. I am confident…
yer
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1 answer

Trying to measure a pulse width and then send pulse of same width using Verilog

I am trying to write Verilog code which will measure the width of a pulse and then send a return pulse which has the same width. So far, I have created a counter which counts the number of periods that the input signal is high. I can then take the…
yer
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1 answer

How do I use command line to compile Libero SoC projects?

I want to use a shell script to compile my Libero projects. How can this be achieved? If anyone has done it, please let me know. The documentation from Libero is not very helpful at all.
gyuunyuu
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0
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1 answer

Top-level HDL File with Libero SOC

I'm using Libero SOC for the first time. I've used Quartus and Vivado before. I notice in the tutorials ways to use the graphical "Smart Design" file type as a top level module. But I can't for the life of me figure out how to set the top level…
FooAnon
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Libero does synthesis again before programming the device

I am using a ProASIC3E PQ208 FPGA and Libero tool to write the vhdl code and program the board on which the FPGA is soldered. When I try to open Libero again to program file, it starts the synthesis again. The old synthesis file exists and I have…
abunickabhi
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3 answers

Using a counter to count how many clock cycles a signal is high using Verilog

I want to use a counter to count how many clock cycles an input signal is high. The issue I am running into is that once the input signal returns back to zero, my counter resets which causes my output to also reset since my counter and output are…
yer
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ModelSim does not run until "$stop" command after editing my testbench

I keep running into this issue where my code stops running before the "@stop" command. This only occurs whenever I add code in Libero and then go back to ModelSim. When I go to simulate in ModelSim, my new code is showing up, however it is stopping…
yer
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