Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [lattice]

Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.

108 questions
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Why is this Verilog RAM modification better in terms of resource usage?

I'm using the open-source toolchain Yosys > NextPnr > IcePack for synthesising code for the Lattice HX8K FPGA. Here's a common version of a 1Kb RAM (that I'm using as Video RAM for a VGA module): module text_ram #( parameter A = 10, …
Hugo Sereno Ferreira
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How the slew-rate and drive strength affect the output signal of the FPGA?

Can someone describe the difference between the drive strength and the slew-rate preferences in Lattice FPGA?
ercegovac
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Trouble with VGA Controller on CPLD

What I am attempting to do is create a VGA controller from a Lattice MachXO CPLD in Verilog. The Problem I am attempting to display the color red with a resolution of 640x480 @ 60Hz using a 25.175 MHz clock internal to the CPLD; however, when I…
Jon.H
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Lattice Diamond gitignore

I am looking for .gitignore file for the Lattice Diamond IDE. I've been trying to only add what I need, but it would be nice to have a .gitignore that just ignores all of the automatically generated files for build/documentation/etc. Yes, I could…
Kris Bahnsen
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5
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I know what a Reset signal is, but a Set/Reset signal? Isn't that impossible?

A schematic by Lattice Semiconductor includes the diagrammed D flip-flop. This D flip/flop accepts, among others, a Set/Reset signal. I would have understood a Set signal. I would have understood a Reset signal. I would even have understood Set and…
thb
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4
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How to read Map-Report in FPGA Synthesis Tools

I have this Map-Report piece product by Lattice Diamond: ... Number of SLICEs: 9609 out of 33264 (29%) SLICEs(logic/ROM): 8814 out of 26460 (33%) SLICEs(logic/ROM/RAM): 795 out of 6804 (12%) As RAM: 795 out of 6804 (12%) …
Luca
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How to properly implement an n-FF synchronizer in Lattice FPGAs?

Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So I have no choice other than write my own synchronizer. In the Xilinx's world I'd use…
firegurafiku
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IO Type (LVCMOS25, LVCMOS18, etc.) in FPGA pins

In Lattice Diamond, spreadsheet view where I assign the signals to pins of the FPGA chip, there is IO type. Restricting the discussion to single-ended CMOS signals, then my choices are given by the voltage level: LVCMOS12, LVCMOS15, LVCMOS18,…
Cal-linux
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What is the purpose of this Verilog code for implementing 3-port Block RAM?

LatticeMico32 (LM32) is a royalty-free CPU that I use to study how a pipelined in-order CPU may be implemented. One particular troublesome point I have trouble with is how the register file is implemented. On a pipelined CPU, you will normally have…
cr1901
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Lattice FPGA - declare pin

I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it is the place where the pin are declare. Can…
MathieuL
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Lattice MachXO2 reset

After reading about GSR/PUR facilities in Lattice FPGAs, I'm still a bit puzzled about how to actually get the proper GSR/PUR-based reset functionality on an actual physical FPGA chip. In the How to Use GSR and PUR application note, they show this…
Cal-linux
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Problem with adding two counters in series on an FPGA

I am using Verilog in Lattice Diamond IDE with a lattice MachXO2 7000HE breakout board. I built a basic counter with a limit input which generates a variable period clock output. It works fine on its own, however, when I add two instances of this…
amfast
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How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3

I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their mind about Altera (mainly down to Lattice devices…
DiBosco
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Arduino to CPLD to toggle an LEDs using I2C

I have a a CPLD (Lattice MachXO2) that echos a signal from an Arduino to turn on an LED. Arduino: //send out .1s pulse on output pin 2 when a 'q' is recieved void loop () { USBinByte = Serial.read(); if (USBinByte == 'q') { …
Ben Elo
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passing Synplify options from Lattice Diamond TCL code

I would like to pass, from the TCL file that is commanding the Diamond tool of Lattice, some options to the Synplify synthesis tool. E.g.: It is possible to set a value of the VHDL generic at toplevel in the…
vermaete
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