Xilinx Integrated Software Environment (ISE) is a suite of design and analysis software for their range of CPLD and FPGA devices.
Questions tagged [ise]
95 questions
17
votes
4 answers
List of Xilinx file suffixes (for ISE)
I asked Xilinx for such a list but they don't have a complete list. I wish to make sure all input files are in source control and all output files aren't. This is with 13.1-13.2 with ISE and PlanAhead
Some of the information they have provide is the…
Brian Carlton
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6
votes
1 answer
Minimal redistributable coregen output for command-line rebuilds
I'm building an SoC with my own soft-core, and I want people to be able to easily rebuild it using Xilinx webpack command-line tools. I'm using coregen's Clock Wizard to create a clock module, but coregen's output doesn't appear to be…
AnthonyGreen
- 163
- 6
6
votes
1 answer
Preventing Verilog module from being optimised away
I have tried to put lots of inverters to stress test my Spartan 6 power supply as recommended here. Here is the basic module:
module inverter(
input wire clk
);
reg [7:0] inverted;
always @(posedge clk) begin
inverted <= ~inverted;
…
Randomblue
- 10,953
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4
votes
1 answer
Why Xilinx ISE can't get access to my custom package?
I am trying to create a custom data type which I am creating in a package using Xilinx ISE 14.5. I am trying to create a generic DEMUX to switch between buses, here is the code of the generic DEMUX:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use…
Andres
- 1,834
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- 51
4
votes
1 answer
How to get rid of the warning "WARNING:PhysDesignRules:367 - The signal IBUF is incomplete."
I'm working on a simple neuron implementation on a Xilinx Spartan-3E starter kit and getting the warning in the topic. Can anyone explain me why I am getting this error?
My code:
module NeuronMdl #(parameter NUMBER_OF_INPUTS= 2) (
input…
scarphin
3
votes
1 answer
Duplication of working PWM signal leads to unexpected behaviour
I am trying to control 13 different servos with my Spartan3 FPGA. For that, I need 13 independent PWM signals generated by my FPGA. The PWM module that I am using works perfectly fine when only one output pin is controlled (instantiated as…
Ahmad
- 41
- 5
3
votes
2 answers
How to connect Spartan-6 with ISE 14.2 on Ubuntu
I bought my first FPGA and I'm trying to implement a simple VHDL program on it, but I don't know how to connect it's Atlys board to ISE 14.2. I'm using Ubuntu 64-bit.
Engine
- 669
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3
votes
1 answer
what is the difference between ISE and Vivado?
I am xilinx ISE and virtex 5 engineer.
I found Vivado something when I ran across the internet.
What is the difference between ISE and Vivado?
Should I have to move to Vivado from ISE?
nashile
- 69
- 1
- 7
3
votes
1 answer
Setting single unused pin in Xilinx ISE
I have a Xilinx CPLD design that I'm not using all of the pins in, however, I have reserved some for future use and bonded them out to a microcontroller. I am defining my pinout in a constraint (UCF) file. I want to set all the unused and…
Joel B
- 3,477
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- 37
3
votes
2 answers
Why does output register remain x in the waveform even when clock changes?
I am using ISE to write my first Verilog code. I wrote a counter:
`timescale 1ns / 1ps
module my_counter( input clk , output reg [3:0] out);
always @(posedge clk) begin
out <= out+1 ;
end
endmodule
I then used ISE to make a testbench…
KFkf
- 215
- 2
- 5
- 12
2
votes
1 answer
Xilinx ISE Prevent Trimming For CPU
I am creating a custom CPU and would like it to be programmable on the fly instead of hard coded in VHDL. The issue I am having is that without initial code for the CPU to run, ISE will trim large amounts of my logic away. I have tried using the…
Proto
- 23
- 4
2
votes
2 answers
Why my FPGA programs does not work?
I am very new to FPGA and sorry for this elementary question. I just made a very simple XOR code like this with Webpack ISE to download to XC2S100 ( just for test!) but it does not work.
EDITION1: According to comments, I checked DONE situation…
Aug
- 1,561
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- 63
2
votes
2 answers
How to assign physical pins of FPGA to Xilinx ISE Verilog modules?
Recently I started learning FPGA programming. I have the " Verilog QuickStart book" and downloaded Xilinx ISE Webpack v14 and watched a number of YouTube videos. At this moment I can build my circuits and test them by the inbuilt simulator but I…
Aug
- 1,561
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- 63
2
votes
1 answer
Xilinx ISE on Debian 10+
I have been working for quite some time now with Xilinx ISE 14.7 on Debian development machines. Before the suggestion comes: We use a Virtex-6 FPGA for our research and have no option to switch to something Vivado compatible (besides, they are…
T0eJam
- 23
- 4
2
votes
1 answer
ISE Design Suite simulation problem
I am new in Verilog language. I am trying to understand the basics. There is this question where the input is a 6-bit number named IN and the output is a 1-bit number named OUT. When IN < 29, OUT is one. Otherwise OUT is zero. I have already written…
Kalamakra
- 173
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