Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [intel-fpga]

A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).

A popular manufacturer of FPGAs (Field Programmable Gate Arrays), such as Stratix and Cyclone, and CPLDs (Complex Programmable Logic Devices), including MAX II and MAX V.

Formerly know as Altera; Intel acquired the FPGA and CPLD manufacturer Altera Corporation in 2015.

Intel FPGA home page

395 questions
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What do HDLs compile/synthesize to?

I'm a software engineer. As a programmer, I have an understanding of what my compiler does for me because I've manually written a close textual representation of what it outputs (e.g. assembly). For precise details of what's output I can look at the…
Jake
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Using both edges of a clock

I am programming an Altera Cyclone IV using Verilog and Quartus II. In my design, I would like to use both edges of a clock so that I can do clock division by an odd factor with a 50% duty cycle. Here is a snippet of my code: always @(posedge…
Randomblue
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Why FPGA's have latches when they are almost never used?

This question is a follow up question of the existing question: "When is using latches better than flip flops in an fpga that supports-both". If use of latches in FPGA's is limited to rarest or rare situations, why do FPGA's have latches at all ? I…
nurabha
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What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24): To manually specify clock uncertainty, or skew, for…
Randomblue
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Do I need to reset my FPGA design after startup?

I usually initialize state registers of my FSMs by specifying an initial value in my VHDL code, so that, I do not require a reset pulse after startup of the configured FPGA. The following example demonstrates this by a "ring-counter" which just…
Martin Zabel
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What are ALMs, LEs and ALUTs?

Does ALM mean "Adaptive logic module"? www.altera.com/literature/ds/ds_nios2_perf.pdf‎ Jul 1, 2013 - One ALUT is equivalent to about 1.25 LEs. Does LE mean logic element and ALUT means adaptive look-up table?
Niklas Rosencrantz
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what is triplication on fpga?

I know FPGA design using VHDL and I came up some new topic recently that usage of triplication in FPGA but I am not confident about its understanding. How can we use triplication in FPGA design and how do we verify this.
srihari
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Altera Quartus "Warning (18236): Number of processors has not been specified...", how to suppress?

My Altera Quartus builds show this warning... Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for…
JimFred
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Improve Quartus partial compile or recompile time

I run Altera Quartus, and I'm using the SignalTap logic analyzer on a Max 10 FPGA. It takes tens of minutes to compile, and every time I'd like to add a signal to SignalTap, I have to compile again. The rapid-recompile button is always grayed out, I…
Voltage Spike
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Altera Cyclone V: Timing issues with routing (interconnect)

I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are timing constraint violations near the DAC interface…
Philipp Burch
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PCIe fails on "polling compliance" state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that the LTSSM (Link Training and Status State…
Randomblue
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Specify exact pin locations on FPGA

I have an Altera Cyclone IV FPGA, and I use the Quartus II software as the compiler. In the "PinPlanner" it is possible to specify groups of pins (e.g. data buses). For each group, an I/O bank and an I/O standard (e.g. LVDS) can be specified. Then,…
Randomblue
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Generating pulse train of varying frequency on an FPGA

I am working on generating a pulse train to control a motor that accepts a pulse train as an input. Each pulse corresponds to a pre-set movement increment; I can set one pulse equal to 1/1000 degree (or whatever), and if I send it 20 pulses, the…
Engineero
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Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I change the JTAG frequency in Quartus II?
Randomblue
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How to properly constrain generated clock and synchronizer in Altera Quartus?

In my Verilog design I have a 25Mhz board clock from which I derive a 100Mhz clock. Coming from an external Pin I have an asynchronous 4.77 Mhz clock which should drive the logic and be synchronized before (using the main clock): always @(posedge…
fhw72
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