Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [hdl]

HDL (Hardware Description Language) is a description language used to describe the behavior of digital circuits. Examples are Verilog, VHDL and ABEL.

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How much does it cost to have a custom ASIC made?

I have browsed several ASIC manufacturer's webs, but I haven't found an actual number. I assume there would be a fixed cost associated with creating masks and such and then there will be a cost per unit. Note: that I don't actually want to have an…
avakar
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VHDL vs. Verilog

VHDL and Verilog are some of the HDLs used today. What are the advantages and disadvantages of using Verilog or VHDL over the other?
stevenvh
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RTL vs HDL? Whats the difference

What is the main difference between RTL and HDL? To be honest I searched / googled it yet people are divided in their opinions. I remember one saying that HDL is the computer language used to describe a digital circuit and when it is synthesizable,…
vvavepacket
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Why are inferred latches bad?

My compiler complains about inferred latches in my combinatorial loops (always @(*), in Verilog). I was also told that inferred latches should preferably be avoided. What exactly is wrong with inferred latches? They certainly make combinatorial…
Randomblue
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How do I learn HDL

I have a course in Digital Design in this semester and just love it. Now I know that most of the work in embedded system and digital design is done on computer simulators first and then implemented using hardwares. So I was wondering how should I go…
Rick_2047
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What happens when an FPGA is "programmed"?

From what I understand, the process of programming an FPGA comes in two parts: Encode the hardware description into bits that the FPGA can understand (i.e. write some HDL and compile it) Load the compiled HDL onto the FPGA. My question is: "What…
Randomblue
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What's the motivation in using Verilog or VHDL over C?

I come from a programming background and have not messed around too much with hardware or firmware (at most a bit of electronics and Arduino). What is the motivation in using hardware description languages (HDL) such as Verilog and VHDL over a…
Reflection
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SystemC vs other HDLs

I am currently involved in a university project to implementing a processor of an existing instruction set. The idea is that by the end of the project I should be able to synthesise this design and run it in an FPGA. Everything is going well so far,…
Andrés AG
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What is a false path timing constraint?

In FPGA world, what exactly are false path constraints for an HDL compiler? Why are they useful?
Randomblue
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Difference between RTL and Behavioral verilog

Can someone tell me what is the difference between RTL and behavioral Verilog code? Is there any clear cut demarcation between designs at these two levels?
Akash Singh
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How to assign value to bidirectional port in verilog?

I'm trying to use a bidirectional port in Verilog so I can send and receive data through it. My problem is that when I try to assign a value to the port inside a task, I keep getting an error. What is the correct way to assign a value to these types…
HzJavier
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Simulating FPGA design without having the actual hardware

I'm new to FPGA and currently taking HDL (Verilog particularly) class. I have sufficient knowledge in digital design like combinational and sequential circuits. I want to create a project similar to the one shown in this YouTube video. I also know…
vvavepacket
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Identifying an edge INSIDE an 'always' block

I am an experienced C programmer trying to learn enough Verilog to create a brushless motor controller. I am nearly done except for one detail. I want to do something like this: reg count; always @(posedge clk, posedge motorruns)begin if("i…
Tinkerer
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Exercise based book to learn Verilog/vhdl?

I was planning on learn an HDL (preferably verilog as I have to take a course in it in subsequent semesters). My initial plan was to first learn the syntax and then implement all the digital systems I studied in my digital electronics course using…
Rick_2047
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Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it. I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am not able to understand a line of code which i saw…
Abhishek Tyagi
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