Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [frequency-divider]

34 questions
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Odd number frequency divider

Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;) I've got this pattern for a frequency divider that divides the clock by 5. It's supposed to have…
LasseValentini
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Divide clock frequency by 3 with 50% duty cycle by using a Karnaugh Map?

In this document, On semiconductor describe how to design a divide by 3 system using a Karnaugh Map: Specify, Divide By 3, 50% duty cycle on the output Synchronous clocking 50% duty cycle clock in Using D type Flop flips and karnaugh maps we…
nettek
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Frequency Divider Analog Circuit issue

I am trying to implement a divide-by-two circuit quoted from the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet Could anyone advise about the spice error "timestep too small" ? div_by_two.asc Version…
kevin998x
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Simple logic circuit to filter out the even numbered pulse?

I need a logic circuit to have a function as shown in the figure: An input signal applied to the input end, I want it to only output the odd numbered pulse and output 0 for the even numbered pulse. To simplify this question, assume the input signal…
Jing
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0 to 999 Hz frequency counter

I'm trying to build a frequency counter with a resolution of 1 Hz that will count any frequency between 0 and 999 Hz and hold that value. I've built the following in Multisim but I'm having trouble getting it to work. The block diagram is the part…
Licentia
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CD4018 divide by 11

I am making a circuit that creates various subdivisions of input frequency by integer values from f/2 down to f/12. Division by 2, 4, 8 are straightforward using JK flip flops. Divisions by 6, 9, 12 can be done via combining divisions by 2 and 3 in…
Ivan Demyachenko
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Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same frequency magnitude? Why make the PLL working at 1:16…
Gianluca G
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CD4521 frequency divider warms up while RESET is HIGH

I have a peculiar problem involving the CD4521 frequency divider of which I use two in a redundant configuration as shown in my schematic snippet below: I noticed that while the devices are held inactive (RESET is HIGH), they both become very warm.…
wheezardth
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Why is a 15 stage binary counter/divider so cumbersome?

There seem to be many ways to take a 32.768kHz signal and turn it into 1Hz. I can use a CD4060, but still have to add a flip-flop... so 2 "large" chips with excess (potentially) unused functions there. Sure the other 4060 outputs could come in…
Jay
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How can I change the frequency of a sine wave from 5 MHz to several smaller ones, e.g. 1kHz, 100Hz and 1Hz?

5 MHz is the frequency of the quartz based oscillator. I get a clean, sine wave output. I would like to (divide) this signal into several, lower frequencies in steps, e.g. 1kHz, 100Hz and 1Hz. I don't want to use a microprocessor but an analog…
Jerzy Przezdziecki
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Custom frequency divider (/timer) question

How can I make a frequency divider with multiple outputs with these conditions: no microcontroller can use up to 4 SOIC-16 chips or up to 8 SOIC-8 (or any combo) can use one crystal/oscillator 9v supply can use one 5V voltage reg. if needed 1 mA…
Bikay
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Why is the 14-stage SN74HC4020/CD74HC4020 binary counter missing 2 output pins, leaving 2 bits inaccessible?

I purchased a few SN74HC4020 ICs, which is a 14-stage ripple-carry binary counter. The SN74HC4020 datasheet shows output pins for bit 1 (pin QA) and bits 4-14 (pins QD-QN). So in other words the output for bits 2 and 3 are not exposed. Why are…
acker9
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Dividing down a VHF signal in a 4046 based PLL loop

I've decided to build a a PLL based synthesiser to produce the Local Oscillator(LO) signal for my DIY transceiver. My aim is to try to use commonly available (preferably inexpensive) parts in what is a mainly educational exercise. I'm a total…
Buck8pe
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Clock divide by 5 - All ICs obsolete?

I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs. For the life of me, I cannot seem to find a single clock divider out there that supports /5 that isn't…
Daniel
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Using a 555 timer and 14-stage binary divider for 2 hour timing circuit

I am researching how to design a timing circuit that will activate a relay with a push button and deactivate the relay after two hours. My understanding is that I can feed the output of a 555 timer to the input of a 14-stage binary divider. Then…
gahigg1
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