Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [fifo]

FIFO (First In, First Out) is one way of managing a buffer for data

FIFO is an acronym for First In, First Out, a method for organizing and manipulating a data buffer, or data array, where the oldest entry is processed first. It is analagous to processing a queue with first-come, first-served (FCFS) behaviour: where the persons leave the queue in the order they arrive.

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Trying to understand FIFO in hardware context

Wikipedia defines the FIFO in electronics as under: FIFOs are commonly used in electronic circuits for buffering and flow control which is from hardware to software. In its hardware form, a FIFO primarily consists of a set of read and write…
gpuguy
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gray code clock domain crossing FIFO fast to slow

I'm trying to understand how clock crossing FIFOs are implemented, and the usual answer I see to convert the read/write address pointers to gray code and then pass through synchronizer circuits into each others clock domain to determine if there's…
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Need for Almost Empty and Almost Full flags in a FIFO buffer

I read somewhere that some implementations of FIFOs have almost full and almost empty flags, the threshold for which can be set by any particular user. It was explained that a need for such flags arises: when you only have an empty signal, you can…
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How can I buffer SPI?

I have a board with a device that outputs data over SPI (as slave device) and a microcontroller. The device signals that data is available (24 bits) by setting a certain pin low, around 8000 times per second. If the data is not read before the…
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Verilog router design and best way to handle variable size packets in verilog?

I have a synthesizable Verilog/logical design question. My question is more logical than syntax. I wish to implement some sort of router that has three input/output ports of full-duplex UART RS232, that are sending packets to each other. Main points…
shush
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Does a 250MHz FIFO chip exist?

If I have 8-bit parallel data being clocked out of a chip at 250MHz, is there some way I can buffer it? I only need to store about 1kB. Preferably this would be a FIFO. Does such a fast FIFO exist at a reasonable price (
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Designing with AC'97 - why does it not have a (FIFO) buffer?

The AC'97 codec seems to dominate the world of digital audio I/O but, what is weird is that it has neither interrupts nor buffers so that it is difficult to interface with a controller, which has other activities. The AC97 demands polling it…
Val
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Metastability Deserialization and clock crossing domain

I have a question on metastability and clock crossing domain. I need to deserialize a bitstream out of an ADC. TXCLK, TXOUT1, INCLK are the outputs of the ADC. So the idea was to register the DATA TXOUT1 on a shift register clocked by TXCLK then…
the dude
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Benefits of RAM vs FIFO in FPGA

If I want to process data in the order it arrives, it seems that a FIFO would be most appropriate; however, I want to look over the data multiple times (at least 20 times), so I am considering either rewriting to the FIFO when I read from it or…
Ethan
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Difference between buffer and mailbox

Peripherals in Micro-controllers usually provide a way for us to send and receive data from it. Usually this are memory mapped registers. I have come across few terminologies. The most often used one is a buffer and probably a FIFO. But when working…
Ravi Teja Gudapati
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Send data from FIFO memory module to USB

I have a FIFO module running at 24MHz, producing 1 byte per clock. Then it produces 24MB/s. I need to send this data to PC through USB or Ethernet. How can I achieve this? Doesn't exist some USB controller or something? Searching in the web I read…
HAL9000
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FIFO wrfull asserted when FIFO is not full

I have an issue with Altera FIFOs. It seems that the full signal wrfull gets asserted even when the FIFO is not full. My FIFOs are of size 8. The SignalTap traces below show the read levels of my FIFOs (rdlevel) as well as the wrfull signals: What…
Randomblue
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FT232H FIFO slow USB?

So, I have an FT232H chip, specifically this breakout. I'm trying to read data as fast as possible from it, so I've set it to synchronous 245 FIFO mode, which the datasheet says should yield up to 40 Mbytes/s. I've wired AC3 = WR# to ground, on the…
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VHDL FIFO w/ RAM

I've been tasked with designing a FIFO in VHDL for the block diagram below. I understand the general mechanism of how a simple FIFO works, but I've been struggling with how to connect the address from the read/write address counter to the address of…
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Asynchronous FIFO design with PULSE synchronizer

I'm trying to understand various implementations of asynchronous FIFO from the following link https://inst.eecs.berkeley.edu/~cs150/sp10/Collections/Discussion/Honors/Honors14_1PP.pdf In the slide 7 there's a proposal where pulse synchronizers are…
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