Electrical Engineering Stack Exchange
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Questions tagged [dram]

107 questions
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How can I implement a very simple asynchronous DRAM controller?

I'd like to know how to build a bare bones asynchronous DRAM controller. I have some 30-pin 1MB SIMM 70ns DRAM (1Mx9 with parity) modules that I'd like to use in a homebrew retro computer project. Unfortunately there's no datasheet for them so I've…
Anthony
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Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM process while manufacturing SDRAM? What differences…
pjc50
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How is a DRAM volatile with capacitors?

There are a few things I understand: DRAM stores each bit of data to a tiny capacitor with some potential difference. Unless the capacitor is connected to low voltage end, the potential difference should remain the same. Why do we need to refresh…
GypsyCosmonaut
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Yields in DRAM and other Massively Redundant Processes

I'm right now combing the electrical engineering literature on the sorts of strategies employed to reliably produce highly complex but also extremely fragile systems such as DRAM, where you have an array of many millions of components and where a…
Mephistopheles
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What determines the ground state of a computers dram?

I have read a paper about the cold-boot attack led by J. Alex Halderman. Full pdf: https://jhalderm.com/pub/papers/coldboot-sec08.pdf The paper shows the decay of a data in memory without power. They used this picture as example: Obviously, the…
dead_values
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Why do DRAMs retain their state better when they are cold (when powered off)?

I'm sorry if this is off-topic. It may be better suited for a computer hardware forum, but I couldn't find anything appropriate. I've been reading about the cold boot method, which can be used in forensic investigations, by enemy governments, or by…
Zen Hacker
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Why are the challenges in using SRAM over DRAM for main memory?

Historically, when compared to DRAM (dynamic ram), SRAM (static ram) is more expensive with a lower density, but it's much faster and more efficient. As a result, SRAM is reserved for devices, such as processor caches and microcontrollers, where…
user148298
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?

Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-oriented, with a burst length of 2bl. I.e. one data transfer…
jayded-bee
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What is DRAM Precharge?

I dont understand what is DRAM Precharge. Is DRAM precharge used for reading the memory, is it applied before reading the row? or is it used closing the row access?
Aakash
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Why are SDRAM CAS latencies so high?

I don't understand why the CAS latency of modern DDR4 memory is so high. I have no trouble understanding why the RAS latency is as high as it is -- given the small amount of charge stored in each bitcell, it is not hard to imagine that it takes a…
Dolda2000
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What is the need for precharging in SRAM/ DRAM memory cell?

Why is precharging so necessary while preforming read operation on SRAM/ DRAM cells? For example in the SRAM 6T cell shown below, Reading 0 requires bit line to discharge to 0; Reading 1 requires that bit line voltage is equivalent to logic '1'…
user5089054
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What percentage of a DRAM cell size is occupied by the transistor and/or the capacitor?

Assuming that we have a 1T1C DRAM cell manufactured at 22nm process. Based on this we can have an idea about the cell area (0.026 um^2 in this case). However, I could not find specific information about the percentage of the area consumed by the…
Arkoudinos
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Why do these resistors decouple the two databuses?

The ZX Spectrum is a computer with a Z80 accessing ROM and two separate areas of RAM, one of which is also accessed by a ULA which generates video. If the Z80 wants to access the video RAM, it may be slowed down to fit in with the timing imposed by…
Lorraine
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No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ODT feature, however Address, Command, Control and…
pcbguy
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What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can someone help me understand those block…
user220456
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