Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [dll]

A Delay Locked Loop, a circuit that uses a voltage controlled delay chain in a feedback loop. The control circuit compares the delayed version of one signal with another signal and attempts to match the edges to make the two signal line up temporally.

9 questions
30
votes
3 answers

What is the difference between a PLL and a DLL?

Phase Locked Loops (PLL's) and Delay Locked Loops (DLL) are used in various applications but there isn't yet a salient discussion of the key aspects of these circuits, how they operate, in what applications they might be used, the comparison between…
placeholder
  • 29,982
  • 10
  • 63
  • 110
4
votes
0 answers

Intermittent control signal injection clock sync

I have a big challenge in my design to overcome: I need clock frequency accuracy of <0.2ppm with incredibly low power consumption. What we are doing currently is, using a 3G transceiver' baseband output, we are using a PLL using the baseband as the…
StuartKerr
  • 41
  • 2
1
vote
1 answer

How to create variable clock frequency source in Cadence Virtuoso?

I am working on Delay Locked loop Project. I want to check the lock range of the dll. I am using vpulse for clock but by giving parameters clock period, clock width, rising time, falling time. It giving the clock pulse with same frequency. I want…
user3244121
  • 21
  • 1
  • 3
1
vote
1 answer

How the delay locked loop (DLL) align the clock?

The delay locked loop is used for align the clock in integrated circuits. In the IC there are no of flip flops and other devices. I want to know that how the DLL align the no of clocks going to different flip flops. Sorry for the wrong English.
user3244121
  • 21
  • 1
  • 3
0
votes
1 answer

Modelling digital DLL for CDR for simulation/modelling purposes only

I have done a Verilog module for clock and data recovery (CDR) using DLL ( this is for simulation purposes only) I used Modelsim for simulation. In the transmitter (Tx), I only have a (clock that has a random phase shift) and random data both going…
Hammam
  • 11
  • 2
0
votes
2 answers

PLL or DLL with controllable phase

I have a clock signal coming from an instrument that I need to use to synchronise other instruments. However secondary instruments need to have different phases and I need to be able to sweep the clock period (100 ns > 10MHz) with 1 ns step…
Raphael
  • 115
  • 5
0
votes
2 answers

Creating a Delay Locked Loop (DLL) on an FPGA

I currently have a delay line using a series of flip-flops and buffers which precisely measures the time between rising edges of a start and stop signal. I would like to implement a delay locked loop (DLL) on my FPGA to help reduce error…
PrematureCorn
  • 558
  • 3
  • 17
0
votes
1 answer

Disadvantages of DLL clock generators compared to PLL

I've been learning from many publications that DLLs offer various advantages over PLLs, such as low-jitter performance and fast locking. So, recently, DLLs have been used for local clock generation in various applications too (edge combining DLL or…
Andrea Toffanin
  • 167
  • 2
  • 6
0
votes
1 answer

Remove time gaps before chip select disabled on FTDI

When using FTDI FT2232H in SPI mode, there are relative short time gaps (~2 ms) between positions where clocks are stopped and chip select is disabled. But if data transmission have high speed rate, in this case gaps may influence. Is there some…
Aave
  • 103
  • 3