Design Rule Checking (DRC) is the area of Electronic Design that determines whether the physical layout of a particular (PCB) layout satisfies a series of recommended parameters called Design Rules.
Questions tagged [design-rules]
50 questions
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Rules and guidelines for drawing good schematics
There are a lot of poorly drawn schematics here. A few times people have actually asked for critiques of their schematics. This question is intended as a single repository on schematic drawing rules and guidelines can point people to. The question…
Olin Lathrop
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The need for SMD neck-down constraints
I am designing a PCB which has +5V input from a USB jack and I want this power trace to be as large as possible to reduce input resistance. While doing my large traces on my PCB tool, one of the stock design rules is giving me an error that my neck…
Alex C
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Update tracks on board to reflect new design rules - Kicad
A PCB has been laid out with track widths according to a set of design rules by net class.
I have modified the net class design rules (Setup → Design Rules... → Net Class Editor) and now I wish to update the tracks on the PCB to reflect their new…
Inductiveload
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Altium Differential Pair Routing Via to Via Clearance
In Altium 14.3 how can one define via to via clearance in differential pair routing to produce a different spacing between via to via and track to track?
I defined a design Rule: Electrical->Clearance->ClearenceViaToVia[IsVia,IsVia] to 0.2mm
Because…
Tom
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Altium: Design rule to highlight a plane that is not assigned to a net
In Altium Designer 20.1.14.287 I tried to create a design rule that would highlight that a plane is not assigned to any net after running the DRC. But in the PCB Rules and Constraints Editor I only find rules for plane clearance and connect…
Thomas
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How should the clearance calculation be on a coated PCB?
How many mm should the clearance be between the A and B pads in the picture below?
And clearance between C pad and D pad?
And clearance between E pad and F track?
And clearance between F track and G track?
Voltage: let's assume 300 volts AC.
PCB:…
johny adv
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Altium - Keepout Area Causing Short-Circuit Warning
I have the following footprint in my PCB library with 6 through hole pads:
When I add the purple keep out area (to either the Keep-Out layer or the top layer), I get a bunch of short circuit warnings when I validate the footprint:
[Warning] …
cvanbeek
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What is the current state of the art design rule for SiC VLSI? Technological impediments to making a SiC microcontroller for a Venus lander at 460 °C?
A sub-discussion below Is there any demonstrated or even proposed technology that can sterilize a spacecraft with 100% certainty and yet leave it electronically functional? in Space Exploration SE involves the speed at which VLSI process development…
uhoh
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KiCad 5.1: where are the design rules?
I'm following the tutorial series on YouTube at https://www.youtube.com/playlist?list=PLEBQazB0HUyR24ckSZ5u05TZHV9khgA1O, specifically the "An Intro to KiCad" videos. I'm using KiCad 5.1.2 on macOS, while he uses an older version on Windows, so some…
Craig S. Cottingham
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Why are power components meant to be power inputs in KiCad?
This was asked before but not answered properly (at least I don't get it). Why are default power components in KiCad libraries are power inputs? What is the idea behind it? I would like connect an IC and some components to make a circuit. My…
Saren Tasciyan
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Altium individual clearance for polygonpour
I want to use a poured plane in my design, but i need more clearance on the bigger pads. If i increase the clearance in the rules, all the spaces between pads, will increase. Is there a way to specify, which pads should have a bigger clearance?
Felix Kunz
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Altium Design Rule - How to apply to one named component?
How can I build an Altium Designer rule that applies to only one component or reference designatorrefdes?
I tried selecting my component, S1, from the Query Helper, but that just puts the string 'S1' into the query. What else belongs there?
Bryce
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Altium: Starved Thermal error
I'm getting the following error on all of my GND vias. Internal Plane 1 is my GND plane:
Starved Thermal on Internal Plane 1: Via (11.002mm,23.798mm) Top Layer to Bottom Layer. Blocked 3 out of 4 entries.
According to this techdoc:…
Plesos
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"Net Antennae Violation" on Pad -> Via -> GND plane connection
I just started routing my first PCB on Altium. It is a simple 2-layer board with bottom layer as dedicated GND plane.
I started out placing GND vias for GND pads of the top layer SMD components like this:
But Altium gives me a "Net Antennae…
Rev
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Final design considerations for LM5143A-Q1 buck converter. Are these features needed?
After a few days of learning how to make a buck converter using the LM5143A-Q1 TI IC, it's finally becoming a reality! This is the final design, highly inspired from page 30 in the datasheet, some values are not yet added. There are just a couple of…
Mito
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