Questions tagged [ddr4]
20 questions
10
votes
2 answers
Why is length matching performed with the clock trace length as the target length?
Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width.
All the high speed PCB design guideline suggest performing length matching with the clock trace length as the target length and trace…
Ananthesh Acharya
- 265
- 1
- 13
5
votes
0 answers
Why DDR4 Specs recommend that Address, Control and Clock buses be referenced to VDD?
Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine):
Timing Budget
Suggested practice is to look at the design from a timing budget
standpoint to provide flexibility in the routing portion of…
mFeinstein
- 4,293
- 11
- 45
- 84
2
votes
3 answers
What are the recommended CK, DQ, DQS, ADDR impedances for LPDDR4?
I am using a micron part with LPDDR4, in many datasheets from micron there are no references to a specific impedance for CLK, DQ, DQS, ADDR. The datasheet mentions that the LVSTL is tuneable, but what is the nominal differential and single ended…
Voltage Spike
- 75,799
- 36
- 80
- 208
1
vote
1 answer
Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
LurenAA
- 11
- 1
1
vote
0 answers
What's the purpose of the DDR4 1X, 2X and 4X refresh modes?
The DDR4 specification defines 1x, 2x and 4x refresh modes as follows:
The default Refresh rate mode is fixed 1x mode where Refresh commands
should be issued with the normal rate, i.e., tREFI1 = tREFI(base) (for
Tcase<=85°C), and the duration of…
geschema
- 433
- 3
- 12
1
vote
1 answer
How do I length match different signal classes for DDR3 or DDR4 routing on a PCB?
DDR3 and DDR4 memory routing can be confusing to for length matching because of the many tolerances and specs of all the different busses.
How do I length match different signal classes for DDR3 or DDR4 routing on a PCB?
Voltage Spike
- 75,799
- 36
- 80
- 208
1
vote
1 answer
What is mean by VREF Training in DDR4?
While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
Selva97
- 533
- 3
- 12
1
vote
1 answer
How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there some standard (e.g. JEDEC-defined) limit to the…
Polynomial
- 10,562
- 5
- 47
- 88
1
vote
0 answers
DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance and length consideration.
what's the reason…
Firas Abd El Gani
- 1,021
- 7
- 15
1
vote
1 answer
DDR4 clock termination
In many places I have seen that an AC termination scheme is recommended for high speed clock termination. What is the reason for choosing this scheme?
For AC termination, can a capacitor be connected to a voltage source or should it always be…
Sumama Hahsir
- 11
- 2
1
vote
2 answers
SPD I2c Address for DDR4 SODIMM
While designing DDR4 SODDIM schematic for a mini-pc motherboard, I understood that I need to set an address to Serial Presence Detect (SPD) EEPROM so the CPU can identify the memory.
While looking at a previous design at a project in my company, I…
Firas Abd El Gani
- 1,021
- 7
- 15
1
vote
1 answer
Termination Regulator for DDR4
I went through a previous Industrial PC Motherboard design in my company where Ritchtek RT9045 was used for DDR4 design. it's clearly recommended tat this device is ideal for DDRII/DDRIII in the features.
I'm designing a PC motherboard which uses…
Firas Abd El Gani
- 1,021
- 7
- 15
1
vote
1 answer
DDRx JEDEC Standard: Retention Time
Different scientific publications [1,2] mention that DDRx memory has a (data) retention time of 64 ms while on average each cell is refreshed every 7.8 us (tREFI). I want to know where this information originates and I was looking into the DDR4…
Patrick
- 121
- 4
0
votes
0 answers
DDR4 ODT vs. POD IO buffer
DDR4 uses POD (Pseudo Open Drain) instead of CTT as its IO buffer scheme and there's only a pull-up resistor for an individual IO in POD.
Is the resistor here also used for DDR4 ODT?
From DDR3 ZQ Calibration, ZQ calibration actually includes…
Wanghz
- 135
- 4
0
votes
0 answers
Behavior of DDR memory address
I'm currently working on understanding DDR4's behavior. I'm referring to the following figure:
As far as I know, x4 architecture will have 4 memory arrays, x8 will have 8, and so on (so the figure will describe an x8 system).
Then, in the figure,…
