Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [ddr3]

112 questions
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Why is length matching performed with the clock trace length as the target length?

Length matching is performed mainly to avoid the skew generated among the parallel data lines/data bus width. All the high speed PCB design guideline suggest performing length matching with the clock trace length as the target length and trace…
Ananthesh Acharya
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Is there a PCB-layout related reasoning behind DDR memory package and footprint?

BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between. Is there a reasoning behind the placement of these pads (in terms of PCB layout), or is this just a consequence of…
SomethingBetter
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DDR3 Data Errors

I am looking for post layout solutions for DDR3 data errors. I have a PCB with a FPGA and a 2 banks (2 rank) DDR3 ram setup. Data errors occur either when the RAM (FPGA is not confirmed, but could be) reaches higher temperatures (40°C) or right…
Eggi
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Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer frequency) is 200 MHz Internal clock rate of DDR memory is…
Sanjeev Kumar
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How many layers at least for proper DDR3 fanout and routing?

I'm working on a project and have been banging my head against the wall for the past couple of weeks with the DDR3 fanout and wiring. I'm trying to keep the cost to the minimum, so I'm using the most cost-effective DDR3 IC's I managed to find, which…
vlex
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Compensating for unbalanced via count in DDR3 routing

I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). All the lines have been routed to the same…
Steinar
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DDR(2-4) Training and Length Matching

Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being sent between controller and memory (presumably…
cr1901
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?

Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-oriented, with a burst length of 2bl. I.e. one data transfer…
jayded-bee
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DDR3 pcb design routing

I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx board schematic as a reference to minimise points…
batyastudios
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Termination resistors with DDR3, are they needed?

I'm using a DSP processor with one chip Micron DDR3 MT41J128M16JT in a project. I read a lot about the termination resistors, but I'm still confused about if I really need those, I didn't start the layout yet, but I can try to match the traces…
Zizo
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waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm also easily convinced that trace length-matching…
lamont cranston
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Using multiple DDR3 controllers on FPGA

We are designing an image processing pipeline on an FPGA which will need the use of memory interfaces at various pipeline stages. Because of the size of the memory required we decided to go with a DDR3 design. It would be really useful if the…
Neville Bamshoe
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No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ODT feature, however Address, Command, Control and…
pcbguy
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PCB - Ram connectors problem

Currently following an schematic for NanoPI NEO4 to make my own RK3399 board. On their schematic for the K4B4G1646D-BCK0,I noticed for pins DQ1-DQ15 on both chips connect to a randomised list of connectors from DDR0_D1 to DDR0_D31 and I was…
Dragonfly3r
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DDR3 routing: swapping data wires

Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization? So, for data lines depends on the correct order? For example connect DQ0 on CPU to DQ1 on memory and DQ1 on CPU to DQ0 on memory. Personally I think…
vlk
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