Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [ddr]

136 questions
23
votes
3 answers

Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A quick search shows that the access time of the…
Arseniy
  • 2,150
  • 11
  • 29
18
votes
2 answers

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge? Are there pros and cons to each?
Ethan
  • 463
  • 1
  • 6
  • 15
15
votes
3 answers

Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is DQS on DRAM chip an output or an input coming from…
pazel1374
  • 864
  • 1
  • 10
  • 24
13
votes
1 answer

Why was full page bursting removed when we moved to DDR

I'm interfacing with SDRAM on an FPGA and full page bursts are a godsend for streaming data. It's seems to be much, much more handy then a fixed burst size. I know it was removed when we moved to DDR. Does anyone know why the most useful burst mode…
John Smith
  • 193
  • 10
11
votes
5 answers

Interfacing with RAM from a PC, e.g. SDRAM / DDR, to a microcontroller

I'm looking into interfacing standard PC form-factor SDRAM or DDR sticks to a microcontroller, but I can't find any definitive details on how they work in terms of how the bus works. I guess it's similar to how any standard SPI or I²C interface…
Polynomial
  • 10,562
  • 5
  • 47
  • 88
10
votes
4 answers

Question about trace length matching patterns for high speed signals

A colleague and I had a discussion and a disagreement about the different ways high speed signals can be length-matched. We were going with an example of a DDR3 layout. All the signals in the picture below are DDR3 data signals, so they are very…
SomethingBetter
  • 2,260
  • 7
  • 26
  • 33
9
votes
1 answer

Is there a PCB-layout related reasoning behind DDR memory package and footprint?

BGA DDR packages have a unique footprint. There are two columns of pads on both sides of the device, and an empty column in between. Is there a reasoning behind the placement of these pads (in terms of PCB layout), or is this just a consequence of…
SomethingBetter
  • 2,260
  • 7
  • 26
  • 33
9
votes
3 answers

DDR1 Layout Considerations - DOs and DONTs

I am novice to high speed design. Before getting in to DDR, I recently learned about impedance matching and how it is done, likewise I learned about length matching and how it is done.(Baby steps towards Signal Integrity) Now, I need to Place and…
V V Rao
  • 1,136
  • 3
  • 19
  • 32
9
votes
2 answers

Why are All DDRs' (DDR, DDR2, DDR3) Internal Clock Set to 200MHz?

If we see the DDR Upgrade technology explain below the internal clock of all DDR is set to 200 MHz. DDR For example,DDR-400 Efficient frequency data bus is 400 MHz True clock rate (IO buffer frequency) is 200 MHz Internal clock rate of DDR memory is…
Sanjeev Kumar
  • 1,474
  • 11
  • 19
6
votes
1 answer

Speed difference between SRAM (Static RAM) and DDR3 RAM

This is more of a computing question, but only electronics geeks would know such things. Today's computers use multiple layers of memory in order to work with data quickly. Currently CPU speeds are anywhere from 10 times to 100 times faster than RAM…
Robin Rodricks
  • 866
  • 4
  • 10
  • 14
6
votes
2 answers

Weird 240 ohm resistor on zq line to DDR

I've been looking at schematics that interface ddr ram and noticed a weird notation for their zq pull down resistor. What is with the dot at the top as well as the 1%? Haven't seen this before.
jack sexton
  • 457
  • 3
  • 14
5
votes
2 answers

Debugging DDR bus issues

We have an SBC board, in the style of the Leopardboard or Beagleboard, that is misbehaving. It's based on the Leopardboard design (TI-DM368 CPU, DDR2 RAM, NAND Flash). Developing software on the leopard all works well. However, the 1st prototype…
John U
  • 7,041
  • 2
  • 21
  • 34
5
votes
3 answers

Is ECC feature in DDR realized with using Hamming code technique?

The fundamental formula for a Hamming coding is as below: 2^k≥n+k+1 Where k = # of parity bits and n = data bits In a DDR system with ECC feature, every data byte will generate an additional ECC bit which makes a byte data 9 bits long. However, if…
Learner
  • 175
  • 11
5
votes
3 answers

DDR3 pcb design routing

I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx board schematic as a reference to minimise points…
batyastudios
  • 133
  • 1
  • 9
5
votes
1 answer

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a suitable time after the start of data lines…
Mihir Patel
  • 51
  • 1
  • 3
1
2 3
…
9 10