Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [cyclone]

Cyclone is a family of FPGAs from Altera

55 questions
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FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless no matter how many characters I send with the…
Rehin
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PCIe fails on "polling compliance" state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that the LTSSM (Link Training and Status State…
Randomblue
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Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I change the JTAG frequency in Quartus II?
Randomblue
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Altera Cyclone V - Linux & FPGA interrupt handling

I need to propagate an interrupt from my custom FPGA IP core to the HPS system of a DE0_nano_SoC (Cyclone V HPS-FPGA architecture) and handle in Linux. I have googled quite a lot to confidently say that this topic is not well covered. Required…
new_stacker
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Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, constraining the timing of all clocks and…
bieux
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Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and connected TMS and TDI pins on the 3.3V VCC instead of…
Arnost
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2 answers

Measuring Power from Altera Dev. Kit (CycloneIII)

The Altera CycloneIII starter kit that I have provides a jumper (J6) that is connected to VCCINT of the CycloneIII FPGA core for what seems to be the purpose of measuring the core's power consumption. Here is the reference page for the kit:…
kbarber
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Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple logic functions. I selected the proper model…
Chris Loonam
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Altera Cyclone IV memory block Verilog module

This document explains the various characteristics of the Altera Cyclone IV memory blocks (known as "M9K"). However, there is no mention as to how these modules should be instantiated in Verilog. Where can I find the M9K memory block Verilog module…
Randomblue
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FPGA non-volatile progamming

I recently bought a Cyclone II FPGA here. I have been able to program it with a USB Blaster cable and the Altera Quartus Software. The problem is that when I disconnect power, I lose the program. How do I program it so it will continue its…
Eric Johnson
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For a PLL Clock multiplier, where does the new clock come from?

If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal and wanted to run my FPGA at 200 MHz, I'd use…
Zephyr
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Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only to the HPS part. Is it possible to use the LCD on…
MA81
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JTAG Design for altera cyclone 3

I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file (http://www.mediafire.com/?0gt55eyperbm385) Or just a snapshot…
Josh Vo
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Why are registers being turned on to 1 before reset/on button is hit on FPGA?

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written: module hello_world( input ron, //reset button (ron = reset/on) input clk, //clk, on…
Lokwill
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How to open up serial terminal for my USB device converter (or, how to enable VCP in linux)?

I am using a new Cyclone V SoC board by Enclustra (Mercury+ SA2) mounted on their PE-1 BaseBoard. To connect to the board serially on Windows platform, I have to connect the board which is detected as USB Serial Device Converter in the Device…
viliyar
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