Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [constraints]

51 questions
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EAGLE Matched Length Pairs / Groups

What facilities does EAGLE CAD have for helping to do layout with matched length groups and differential pairs? Can you apply such a constraint in the auto-router? As a follow-on to this, what (other) free Electrical CAD tools support this type of…
vicatcu
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ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd like to ask the EE community for help with some…
FriendFX
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Op amp analysis: when are the "negative feedback rules" applicable?

When we build op amp circuits that use negative feedback, like so: ... we can analyze the circuit very easily, by assuming that $$v^- = v^+$$ due to negative feedback (when also assuming the op amp is ideal, of course). Besides the obvious…
exscape
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ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd like to ask the EE community for help with some…
FriendFX
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1 answer

Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results

Overview I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed in simulation only. I have the following entry in…
drxzcl
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How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my external circuit has? What I hopefully understood…
SDwarfs
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Analog Video PCB Layout

What special considerations and/or constraints are typically applied when routing analog video signals on a PCB (e.g. VGA, NTSC, etc). I'm thinking try and keep them routed on a single layer (i.e. at most 2 vias), try and keep a ground plane under…
vicatcu
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Fix Conflicting IO Standards

I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD. You can find all of the IOSTANDARD's available for Spartan-3E in this document. Whenever I try to compile my project it…
MLM
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Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in one clock cycle (i.e., double data rate, DDR). simulate this circuit – Schematic created using CircuitLab Which may be the result of synthesizing the…
mkrieger1
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Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. Still, when I have to code them in a sdc file I…
Giancarlo Sportelli
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How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this module are multidimensional arrays. For…
Matt B.
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Best practice to constrain dynamically tuned FPGA->DAC data path

Data is moved from the Zynq 7010 to AD9779A DAC using parallel SDR link at 155.52MHz. This DAC generates DATACLK clock that is used to clock data out of the FPGA (see picture for the relevant FPGA design part). The DATACLK signal can be delayed…
Oleg Skydan
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How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are "born", they are MUXed, and we call this generated…
Light
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SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining bits. This arrangement causes a setup violation…
HypeInst
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Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) sends out a 3-wire SPI interface to 4…
CanisMajoris
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