Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [code-design]

16 questions
25
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2 answers

C coding design - function pointers?

I have a PIC18F46K22 and program it with the XC8 compiler. In the end, I'll have a system like a pc with stdin and stdout. So in the main loop there will be a function which is checking if there is new input. If there's input, a function will be…
user17592
11
votes
2 answers

Difference between If-else and Case statement in VHDL

I want to understand how different constructs in VHDL code are synthesized in RTL. Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL…
nurabha
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11
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5 answers

Do open source libraries exist for VHDL the way they do for C++ or python?

When I'm approaching a problem in C++ or python, there are many libraries that exist which do the heavy lifting of my code. I'm thinking about GNU GSL, BOOST, or FFTW for C++, and NumPy or SciPy for python. In many ways, the fact that these…
Sam
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8
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2 answers

Flow diagrams for embedded applications

I have embedded application which uses interrupts and dma. The main loop only sends data to PC. How to design flow diagram of program? How to show interrupts and dma working on flow diagram? I've found several topics in google about embedded uml…
krzych
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2
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3 answers

How to transmit ASCII over RS-232?

i want to display the voltage level through a Potentiometer over the serial comm line(RS-232) in pure ASCII. I am trying to do this using MC9S08AW60 on the Board-DEMO9S08AW60E. So, if the potentiometer is at 50% position, on Hterm it should show as…
sheetansh
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2
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2 answers

Verilog: Change a Certain Delay According to the Current Output

For Verilog 2005, when writing the test bench, is it possible to create a lookup table of delay values, and then assign a certain value in it to be the delay of some procedural block? For example: reg clk; reg [9:0] delay [0:15]; //suppose…
user61665
2
votes
1 answer

Synchronizing multiplier with adder to form mac

I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the two to make an 8 bit multiplier accumulator, but…
titan
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1 answer

MSP430 Coding, Can I Place an Interrupt Vector Inside a Function?

As the title said, I am trying to see if an Interrupt Vector can be embedded inside a function? I am using IAR, but gcc or ccs would work too. I don't see it done in any code online. Example: void function_funtime (int test){ int lm4970_state =…
Passerby
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3 answers

Can someone help me complete this Verilog code for this sequential circuit?

I'm still pretty new to Verilog and all and could use some help completing/fixing my code for this problem. I have made the state diagram, state table/assignment, minimized the equation, and even have some of the Verilog done, but I'm just not too…
ModdedLife
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Structure Identification in HDL codes

I wanted to automatically Identify some structures in HDL code (Verilog/VHDL), let say an adder. I need to automatically detect how many adders in the design. I am not sure from where to start, should I like convert my code into AST (abstract syntax…
Hachani Ahmed
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0
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1 answer

Performing different actions on the same timer

I am working with MC9S08AW60 on the Board-DEMO9S08AW60E. I have written the following code to perform Serial Comm, LED sequence and Keyboard Tx-RX. for(;;) { int i =0; if(TPM1SC_TOF == 1) { // this part shows the percentage…
sheetansh
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0
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4 answers

Can binary code such as an embedded OS or user application code be stored using silicon physical gates

Hello as the questions describes I'd like to know whether it's possible to do this ? Can binary executable code which is executed by a processor core possibly be stored using physical silicon gates ? I understand that a device's OS or user…
VictorM
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2 answers

Avoiding multiple defines by using side effect of PIC banking

This is more a question of style than anything else and might strike some as a bad thing to do. If I have a serial port pin on RC4, say, I can make some defines to help out: #define TXSER_PIN LATC, RC4 What I realise then is that you can do…
carveone
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3 answers

How to determine an expression that detects underflow?

This is a part of my computer science assignment: When adding two unsigned binary integers, an overflow can easily be verified by observing the carry out. Specifically, an overflow occurred if and only if S' · Cout = 1. Does anybody know what this S…
Mxxx
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2 answers

verilog state machine - state won't update

So I'm trying to simulate a state machine with outputs s and v and a state. for some reason our s and v values are updating but the state refuses to change, any help would be awesome module controller( input x, input clk, output reg S, …
greenteam
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