Clock Domain Crossing. Used where information is transferred from synchronous logic from one clock source to synchronous logic using a different clock source.
Questions tagged [cdc]
50 questions
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How does 2-ff synchronizer ensure proper synchonization?
Using 2-ff synchronizers has been a standard for a signal to cross clock boundaries. And there are lots of paper/figures illustrating the mechanism, such as this one:
It seems bclk can only sample the pulse of adat once (at the second rising edge of…
fiedel
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gray code clock domain crossing FIFO fast to slow
I'm trying to understand how clock crossing FIFOs are implemented, and the usual answer I see to convert the read/write address pointers to gray code and then pass through synchronizer circuits into each others clock domain to determine if there's…
user2913869
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cross clock domain databus
I asked a question some time ago about crossing clock domains
Design practice crossing clock domains and async signals.
One of the "rules" is to never synchronize multi-bit signal bit-by-bit, because of timing glitches between individual bits.
I…
JakobJ
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Design practice crossing clock domains and async signals
I have been designing a few projects on different FPGA's in VHDL, and it seems my most common source of "hard to find errors" is when I forget to synchronize an async signal, or forgets to resync a signal crossing clock domains.
My best weapon so…
JakobJ
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Do I need a clock crossing circuit for signals clocked by mirrored PLLs?
Assume that within an FPGA, I have two data streams that are being driven by two clocks. The two clocks are generated by 2 physically separated PLLs (still within the same FPGA), both of which have the same single input reference oscillator, and…
Sittin Hawk
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Clock Dividers with Clock Domain Crossing
I am doing a design in FPGA that looks like this:
100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with flip flops. I thought of not using PLL to make my…
Meenie Leis
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Metastability error propagation with flip flop
I do have a confusion regarding the metastability resolution using flip flops , I know that I should add synchronizer of two or three d-flip flop to guarantee a safe transmission at clock domain crossing boundaries, but my confusion is that the…
Hachani Ahmed
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CDC Synchonisation primitives for an Altera FPGA
I am working on my first non-trival FPGA design and finally have a need for Clock Domain Crossing (CDC).
There are multiple resources (amongst others) which discuss various architectures for CDC and some related questions. The theory is fine, but…
Damien
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How to properly implement an n-FF synchronizer in Lattice FPGAs?
Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So I have no choice other than write my own synchronizer.
In the Xilinx's world I'd use…
firegurafiku
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questions about up-sampling and moving from slow to fast clock domain in FPGA
I encountered some questions and problems I asked myself lately and hoped I can get a nice lead here before I start reading long articles without even be sure if it's the right way.
Let's assume I have an FPGA design, where I get ADC data with a…
Michael Rahav
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Clock Domain Crossing for Pulse and Level Signal
For pulse we use Pulse-Synchronizer and for Level Signal we use 2-flop synchronizer but what if the signal can be of Pulse or Level behaviour. Is there any way to synchronize that?
EDIT:
After @Paebbels's answer, there is modification in Circuit, it…
Prakash Darji
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3
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Clock domain crossing timing constraints for Altera
I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
As I understand it this will cause all signals from clk_A to clk_B to be treated as false…
AxelOmega
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Is it true that for asynchronous clock domain crossing, there is always a small chance that data will be lost or corrupted?
There are several techniques that can be used to transfer data between two asynchronous clock domains. For a few bits, and depending on direction of data between the two clock domains, one could use register chain for slow -> fast domain and use…
quantum231
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How to calculate the number of required flip-flop stages needed for clock-domain crossing?
In a given scenario where I have two clock domains driven by a 200MHz and a 30 MHz external independent clocks, what would be the best way to calculate the number of flip-flop stages needed for proper clock-domain crossing?
At the moment, I'm…
nanoeng
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Why 1.5x ratio limitation for synchronizing slow signals into fast clock domain?
Why 1.5x ratio limitation for Synchronizing Slow Signals Into Fast Clock Domain ?
kevin998x
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