Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [cadence]

For anything related to Cadence: EDA Tools and IP for System Design Enablement

181 questions
7
votes
2 answers

How to convert files from Cadence to Eagle CAD?

Is there any free software that can convert Cadence files (.dsn, .opj, .brd) into Eagle CAD files (.brd, .sch)?
Angs
  • 3,275
  • 8
  • 33
  • 54
6
votes
3 answers

Verilog Netlist format with "\"

After synthesizing my RTL level design into verilog netlist, I find the syntax confusing. Here is what I mean. RTL compiler gives me: MUX2X1 g11005(.A (n_741), .B (\in_a[9] ), .S (n_2197), .Y (n_1063)); What is "\in_a[9]"? XST gives me: wire [1…
drdot
  • 447
  • 7
  • 21
6
votes
1 answer

Why Cadence not revealing their prices for their software product?

I contacted the Cadence office as a PhD student and also a faculty member to inquiry their price for an academic license. After 8 emails back and forth I noticed that they are not willing to answer the simple question of how much we have to pay to…
Dr. Ehsan Ali
  • 862
  • 2
  • 10
  • 24
6
votes
2 answers

how to see dc operating region names in cadence DC annotation for MOSFET

How do I see the operating region names like "active, saturation" in cadence for MOSFET. I remember getting it by setting up View> DC annotation> Setup > selecting DC operating region > Display > region. But Now I am getting the region displayed as…
AAI
  • 242
  • 1
  • 3
  • 15
4
votes
2 answers

Phase margin is 90° but transient step response shows overshoot

The Bode plot of the loop is as shown here: The transient step response looks like this: The block diagram looks something like this - basically a single stage op-amp (OPAMP in figure) with high gain (cascode structure) biasing a FET (M1) such…
SBO
  • 53
  • 4
4
votes
0 answers

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in one clock cycle (i.e., double data rate, DDR). simulate this circuit – Schematic created using CircuitLab Which may be the result of synthesizing the…
mkrieger1
  • 143
  • 7
3
votes
0 answers

PSpice VSIN frequency - how to set it in rad/s?

I know, that if I want to set FREQ, I need to set it in Hz, not in rad/s. I know, that 1 Hz = 2*pi rad/s, but how to do this in PSpice? What should I enter exactly? and btw. if I want to set VOFF (voltage offset), I need to pass it in volts, not an…
TomDavies92
  • 173
  • 2
  • 9
3
votes
3 answers

Designing Schmitt trigger oscillator using CMOS NAND gate

I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology. Question: it can be seen in the…
Bam_Khel
  • 71
  • 4
3
votes
1 answer

How to compare Matlab/Theory <=> Cadence: Switched-cap. Integrator: Mag & Phase

I tried to compare the simple switched-capacitor integrator below, between Cadence and Matlab (at the end acting as a simple loop-filter for a delta-sigma). I am stuck now on the point of how to compare the 2 results CORRECTLY, because of the…
bernd2700
  • 91
  • 4
3
votes
0 answers

Reducing the offset voltage of a source follower

I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range. I have a few constraints for this task: I can use nmos, pmos and pmos4 but can't use nmos4 as the fabrication process…
Oreoluwa Adesina
  • 31
  • 1
3
votes
4 answers

How do I observe a PLL's frequency tracking once the lock has been acquired?

I am trying to design a basic PLL (second order-type 1) to understand its dynamics. I am using Cadence Virtuoso for simulations. I have designed a voltage controlled oscillator that has a center frequency (at Vcontrol = VDD/2) of 16MHz, an XOR phase…
JGalt
  • 867
  • 2
  • 21
  • 38
3
votes
1 answer

Encounter: Hold time violation on clkgate

I'm trying to get rid of a clkgate timing violation. I have two of them and those are really big violations as you can see in this report: +--------------------+---------+---------+---------+---------+---------+---------+ | Hold mode | …
Gp2mv3
  • 131
  • 5
3
votes
1 answer

How to add two output expressions to calculate the third expression in Cadence icfb 5?

I am trying to calculate the average propagation time carry_TP from carry_TPHL and carry_TPLH which I already got the expression from the calculator tool and works well. Now how do I make the third output expression for carry_TP =…
dr3patel
  • 1,620
  • 3
  • 22
  • 31
3
votes
3 answers

Connecting copper pours in Cadence (OrCAD) PCB Designer

I'm trying to climb the Cadence learning curve, coming from an Eagle background. My board is four-layer, with a ground plane underneath the top layer. I have a surface mount IC that has an exposed pad, which should be soldered to ground. I want to…
bitsmack
  • 16,747
  • 9
  • 52
  • 108
2
votes
1 answer

Programmable FGMOS’ simulation model using Virtuoso

I know that one can introduce programmability in FGMOS transistor using Fowler-Nordheim Tunneling and hot electron injection, but am unable to implement this idea in cadence design tool virtuoso. I would like to know how to generate this equivalent…
user34979
  • 21
  • 1
1
2 3
…
12 13