Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [cache]

Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.

Cache is a type of memory used by the central processing unit (CPU) of a computer to reduce the average time to access data from the main memory. The cache is a smaller, faster memory which stores copies of the data from frequently used main memory locations.

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Can a CPU function with nothing more than a power supply and a ROM, using only the internal cache as RAM?

Can a CPU (such as the Intel i3/i5/i7/Xeon) with on-chip cache RAM use that as its only functional RAM, without any external memory banks attached? Or must there be external RAM, and the cache cannot be accessed or used alone? Modern desktop/server…
Dale Mahalko
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How can cache be that fast?

Here is a screenshot of a cache benchmark: In the benchmark the L1 cache read speed is about 186 GB/s, with the latency being about 3-4 clock cycles. How is such a speed even achieved? Consider the memory here: the theoretical maximum speed is 665…
Knight
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Are page table walks cached?

On a microprocessor with hardware TLB management (say an Intel x86-64) if a TLB miss occurs and the processor is walking the page table, are these (off-chip) memory accesses going through the cache hierarchy (L1,L2,etc.)?
ritter
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Why is L1 cache faster than L2 cache?

I'm trying to understand why certain CPU cache memories are faster than others. When comparing cache memory to something like main memory, there are differences in memory type (SRAM vs DRAM), and locality issues (on-chip vs having to traverse a…
ConditionRacer
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Is there a correspondence between cache size and access latency?

Is there is a correspondence between cache sizes and access latency? All other things being equal, does a larger cache operate slower? If so, why? How much slower?
ivanmp
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stack cache instead of registers

Is there a processor that do arithmetic operations on a stack and not on registers? To keep performance, of course, that processor should cache top block of a stack in the same type of memory that is used for registers. I read in a paper (David R.…
beroal
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently used data items (such as elements in an array or…
MartinX
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How to best understand cache associativity?

AFAIK this definition is the most clear and physical: Associativity number = Number of comparators. Is it correct? Could you make a more precise / better definition? The wikipedia illustration is somewhat difficult to look at:
Niklas Rosencrantz
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Difference between 2-way and 4-way caches?

I don't fully understand this picture: If the data and instruction caches are separated, doesn't that mean that this CPU is not von Neumann model but Harvard model? And what does it mean that one cache is 2-way and one cache is 4-way?
Niklas Rosencrantz
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What is the meaning of this line? "Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity."

Memory-mapped, cached view of external QSPI flash. The cache is specified as 32 KB with 4-way associativity. Does it mean that my external QSPI Flash is only 32Kb or it has been memory mapped onto 32Kb? Does cached view mean that repeated read…
MaNyYaCk
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Why do we need the MOESI/MESIF protocols?

As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line. But, in the MESI protocol, only one cache can have a cache-line 'A' in the modified…
Anish Ramaswamy
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Processor - L1 Data cache interface

Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer: I'm writing a simulation model of a multi-processor…
Neha Karanjkar
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Controller Resets after Enabling Cache

I am using a MCF5253 controller which is based on Coldfire Architecture. It has 8KB of Instruction Cache. Everything was working fine till I enabled it's Instruction Cache. Now what's happening is Adapter is getting reset randomly. When I debug it,…
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Virtual Memory, Cache, and TLB's

I recently asked this question over at stackoverflow, but I was told by a user that it was off-topic, so I am posting it here since it's more of a hardware question. I'm trying to study for an exam and I'm trying to answer the question below. I'll…
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How many bits are used for the tag, block, and offset fields for the representation of a memory address?

A small byte-addressable embedded computer system, with a word length of 32 bits, has a main memory consisting of 4 KBytes. It also has a small data cache capable of holding eight 32-bit words, where each cache line contains only two words.…
Niklas Rosencrantz
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