Questions tagged [boundary-scan]
14 questions
9
votes
6 answers
Boundary scan developer and testing tools
I have to choose a tool for production testing of fairly dense PCB's with 4+ FPGAs 10+ DSPs, ethernet controllers and PCI controllers.. Does anyone have any experience with any of the tools available from GOEPEL, XJTAG, Jtag-technologies or if…
Keh0082
8
votes
3 answers
JTAG boundary-scan test software to view and control pin states
What inexpensive or free tools could you recommend to view and control pin states via JTAG boundary-scan?
I'm aware of full-featured boundary-scan products that cost tens of thousands of dollars and used in manufacturing houses mainly. I want a…
rapanui
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6
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1 answer
Using JTAG to "explore" a board without damaging it?
I have one Amontec JTAGKey2 Generic USB JTAG cable interface. What I am looking for is some explanation of how to "explore" a device of which I don't know all exact details, but for which I have a BSDL file that fits almost. I cannot damage the…
0xC0000022L
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6
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1 answer
MSP432 Programming and boundary scan issues (4-Wire, 2-Wire and SWD)
I have reached a predicament.
I have a production board with an MSP432 that will not program. To provide some context, I am using the XDS110 that is supplied with the MSP432 launchpad and am simply running jumper wires (approx 10cm) to the target.…
Nitrousoxide
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5
votes
4 answers
Boundary scan - High speed interfaces
I was given the task to evaluate existing boundary scan systems. At this moment, we are using a simple solution which allows us to define boundary scan vectors which we can check. This is fine for simple tests and is perfectly integrated into our…
Tom L.
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3
votes
1 answer
How can pin states be altered by using JTAG Instruction Codes?
There are several mandatory JTAG instructions to use for boundary scan. I have learned, we can change pin states of MCU or CPU by using that instructions. However, I could not find any detailed information about it. How can I change pin states with…
MIrchhh
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1
vote
0 answers
Boundary scan current
I'm designing a test PCB containing a CPLD that's going to be used for boundary scan. I'm now calculating how much power the circuit will draw and wonder if/how the boundary scan cells interact with the IOs of the CPLD. Is the current sourced/sinked…
SpaceGuyGabe
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1
vote
1 answer
How to test Ethernet PHY's MDI interface through JTAG Boundary scan
We now use SCANWORKS Boundary Scan Tool from ASSET to make Ethernet SWITCH's manufacturing test. But in almost all PHY chips from broadcom corp, the MDI interfaces are "Linkage" bits. It means that there are no Boundary-Scan Cells(BSC), so we could…
Steven Chen
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0
votes
0 answers
When to use IEEE1687 vs IEEE1500
I'm curious as to the use cases of IEEE1500 (ECT) and IEEE1687 (IJTAG).
From what I understand you can have a IEEE1500 Wrapper that is IEEE1687 compliant, but I've been seeing that IEEE1500 is typically for "complex" cores (which I would assume to…
0
votes
1 answer
Need for double latch design boundary scan cell
The book System-on-Chip Test Architectures, Wang et.al. mentions the need of double latch based design on boundary scan cell.
"The bidirectional buffer illustrates the need for the double-latched scan chain design
of the basic BSC to prevent back…
spaul
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0
votes
1 answer
Modelling an STM Tip current
As part of a current-to-voltage preamplifier that I'm working on improving, I'm trying to model the current source of an scanning tunneling microscope (STM). The way it works is described below (based on my understanding), with the block diagram…
BestQualityVacuum
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0
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0 answers
Where can I find IC packages list wich used in BSDL files?
I try to read a BSDL file. For example I take this. Then I change EQFP144 to TFBGA296 in this place:
attribute PIN_MAP of MAX_10_10M02SCE144 : entity is PHYSICAL_PIN_MAP;
constant EQFP144 : PIN_MAP_STRING :=
--I/O Pins
After this I load the BSDL…
Arseniy
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0
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1 answer
Is there a way to convert BSDL format to synthesizable verilog?
I have a BSDL file for a device for which I need to generate test patterns through an FPGA. I learnt that BSDL is a subset of VHDL but the file looks like it describes the hardware of the DUT. I know this file is interpreted by an ATE which I don't…
Pramod
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0
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Why is there need for both functional validation and LBIST during Post-Silicon?
In Post-silicon testing, we have a functional validation testing where C tests are developed to verify the functionality of the SoC, through a JTAG interface connected to the PCB TAP and controlled through some software like Code Composer Studio.…
Shankhadeep Mukerji
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