Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [boolean-algebra]

In mathematics and mathematical logic, boolean algebra is the branch of algebra in which the values of the variables are the truth values true and false, usually denoted 1 and 0 respectively. Boolean algebra is used in the analysis and simplification of digital (logic) circuits

453 questions
36
votes
5 answers

How did people realize they could do logic with electronics?

How did people realize they could do logic with electronics? Are there anecdotes or records of the first realizations? I'm wondering about the first "eureka" moments.
Kinnard Hockenhull
  • 485
  • 4
  • 4
25
votes
7 answers

What will happen if the output from a NOT-gate injected- BACK to its OWN input?

Not-gate, if get a 0(Off) input, it gives an 1 (On) output. And if get a 1 (On) input, gives-back a 0(Off) output. Now, if-I could bring the output back to the input of the not-gate, then what will happen? If the gate is getting a 1 input, it is…
Always Confused
  • 1,591
  • 6
  • 25
  • 49
23
votes
4 answers

Why is the + sign commonly used as logic OR operator?

A few days ago I was asked, why it is pretty common to use the + instead of the v symbol as the boolean OR operator in digital logic. His argument was, that it is totally counter intuitive to use + for OR, because it is more likely to be interpreted…
Rev
  • 10,017
  • 7
  • 40
  • 77
16
votes
7 answers

Why does F + F' = 1?

I have the function: \$f(x,y,z,w) = wx + yz\$ I found its complement function to be: \$f '(x,y,z,w) = w'y' + w'z' + x'y' + x'z'\$ I have to show that: \$f + f '=1\$ but I can't see how to do it. It seems as if there just isn't anything that…
Carl
  • 3,646
  • 1
  • 14
  • 33
15
votes
4 answers

Digital Logic circuit - exam question

I have a question from exam that I failed to solve: I need to build a digital logic circuit that is receiving 4 bit number and return true if the number is 0, 7 or 14. I have only one XOR gate (2 inputs), one NOR(3 inputs), one NAND(2 inputs) and…
nrofis
  • 252
  • 1
  • 10
12
votes
6 answers

My Professor and I are debating about absorption law

So the question is \$(w+y)(wz+wz')wy+y\$ and this is my answer by absorption law where \$A+AB=A\$: $$ (w+y)(wz+wz!)w y + y\\ B A + A $$ So the answer is \$A=y\$. My professor said I was wrong on using the identity because the long…
Ryan
  • 159
  • 6
9
votes
2 answers

What is this trapezoidal logic gate?

What is this thing called? how does it work? I've tried googling so much, even pasted the image in the google search box haha Its used here on the MSP430:
Jered
  • 93
  • 1
  • 6
9
votes
4 answers

Determining minimum number of NAND/NOR gates required to realize a Boolean expression

Is there any algorithm to determine the minimum number of NAND or NOR gates with given number of inputs availability / unavailability of complemented input required for realizing a Boolean expression? We can get an AND-OR form as prime implicants…
Samik
  • 141
  • 1
  • 1
  • 6
8
votes
2 answers

How to map a truth table to ternary logical functions?

Please be kind. I have a thorny and important question from a different field of engineering whose answer may be fairly well-known in electrical engineering. I asked a similar question on StackOverflow Suppose I have a truth table of 5 inputs and 1…
HJLebbink
  • 151
  • 1
  • 12
8
votes
3 answers

How do you implement the following function using nothing but 2:1 MUX?

I am having difficulties understanding how to implement boolean functions, particularly given that I may only use 2:1 muxes and the variable D as a residual variable. The function is as follows: $$ F(A, B, C, D, E) = \sum ( 6, 7, 12, 13, 14, 15,…
user1969903
  • 211
  • 1
  • 2
  • 9
7
votes
3 answers

How to build a 3-input NAND gate from 2-input NAND gates or a 3-input NOR gate from 2-input NOR gate?

For NAND, I am doing a truth table for it and then truth tables for all the possible combinations, but as you can see the process is very long and I am still yet to get an answer. Same goes for NOR gate. How do you go about it?
studious
  • 379
  • 3
  • 8
  • 16
6
votes
1 answer

Minimizing logic expression for two-input NAND gate implementation

I have recently been struggling with this homework problem that is requiring minimization of a logic expression to be implemented using all NAND gates. The problem requires a very small number of NAND gates, and I am finding it impossible to reduce…
armencm02
  • 69
  • 2
6
votes
2 answers

Build circuit from a formula

I've this formula: y = AB + AB'C + A'C I've to build a circuit with only a 2:1 mux and a OR port. I've done the truth table and k.map, but i've not idea how proced. EDIT: @jonk Thanks for your time and for an exaustive and complete answer. It's…
Andrea Angelini
  • 63
  • 4
6
votes
2 answers

Minimizing(optimizing) digital logic circuit with multiplexer(s)

(this by the way was an exam question) For \$F = \sum m(2, 3, 5, 7, 11, 13)\$, I am trying to implement a digital logic circuit using only the following: 2:1 MUX (cost: 12, and must use at least one 2:1 MUX) 2-input AND gate (cost: 6) 2-input OR…
L J K
  • 107
  • 6
5
votes
4 answers

How to optimise Boolean functions in very many variables?

Given a black box with N binary inputs and specification of the output for every one of the 2**N possible input states (but no pre-knowledge of the logic in the box) I need software tools to design the minimal gate logic in the box. What method or…
cuddlyable3
  • 468
  • 2
  • 10
1
2 3
…
30 31