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Questions tagged [axi4]

Question related to the Advanced Microcontroller Bus Architecture (AMBA) based Advanced eXtensible Interface (AXI) protocol. This interface is commonly used in a lot of present-day SoC's

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How to implement an interconnection matrix in VHDL?

I was reading through the documentation of the AXI standard when I came across the interconnection matrix shown below. In short, the interconnection matrix provides a path for several masters to connect to several slaves at the same time. If there…
Leonhard Euler
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What happens when there is a simultaneous Read and Write launched to the same address in AXI3/4?

I have a doubt regarding the AXI3/4 protocol. Assume a hypothetical scenario where a single master issues a valid Read and Write transaction to the same address simultaneously. From the AXI specification, I understand that there is no…
Rajesh Shashi Kumar
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AXI: Restrictions on slave address spaces?

Does the AXI specification impose any restrictions on the address space of slaves? I've read the latest version of the AXI specification (chapters A1-C2, ARM IHI 0022H) and could not find anything explicit. The most I could find was the following…
MuchToLearn
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What does the T stand for in AXI4-Stream's TDATA, TVALID, TREADY, etc.?

In the AXI4-Stream protocol, the names of the signal that make up a stream are prefixed with T: TDATA, TVALID, TREADY, TLAST, etc. Does the T prefix have a meaning? "Transfer" comes to mind, but that term is also used in the (non-stream) AXI4…
Martin
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Software Driver for custom AXI-stream IP in Xilinx SDK

I created an IP (say 'myip') using HLS with AXI-stream input and output. After connecting the IP to Zynq and exporting the bitstream to SDK, header file xmyip.h got generated which had functions like "Xmyip_LookupConfig", "Xmyip_CfgInitialize" etc…
user3219492
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AXI4 communication over Chip2Chip and Aurora

I am trying to exercise the communication between AXI4 master and slaves over the Chip2Chip IP core. When I have a master in one design and the slaves in the other, everything works fine - I properly access both slaves as shown below. However, if I…
Nazar
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Determining AXI4-stream Data FIFO size, understanding Packet Mode?

I want to take a standard AXI4-stream Data FIFO IP core and use it for data frame encapsulation for both the Ethernet and TCP/UDP layers. When packing a header onto the packets, I need to know the length of the packet itself. Let's say I'm getting a…
comc cmoc
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AXI WSTRB and AWADDR issue with overlapping writes

I am having issue with AXI Protocol Checker pc_status[22] AXI_ERRM_WSTRB . Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and Beat Number. What does it mean by The information…
kevin
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Interpretation of pc_status bit location from Xilinx AXI Protocol Checker IP

In the pc_status error bit location , is it bit #32 because in the following simulation waveform, BVALID is never asserted high during the time when pc_status error bit #32 is asserted ?
kevin
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Relationship between AWVALID and WVALID in AXI4-Lite interface

I am implementing an AXI4-Lite slave interface in FPGA and I want to have the read/write operations to complete in as few clock cycles as possible. With that in mind, can I assume any specific relationship between AWVALID and WVALID coming from the…
rvkrysh
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How does the master determine that the data has been completely sent from slave in AXI protocol?

The reason why a read response channel is not needed in 'read' is that if the slave doesn't send data, it can be considered that all the data has been sent. In cases where data might be interrupted, arrive out of order, or be interleaved — where the…
Carter
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How to properly retrieve information from an AXI4-Stream interface?

I have got a module with an AXI4-Stream interface. I want this module to extract an ethernet frame from the incoming TDATA signal in order to change some of its fields and send it forward to the output. The issue is that the frame is bigger than…
anmomu
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How different layers of cache connect in hardware?

I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions: Does the unified L2 Cache have dual port (one for L1I another for L2D) or single port? If…
Johnson_NCKU_EE
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What is the rationale behind enforcing WDATA ordering in AXI3?

While trying to understand the AXI protocol,I came across this: Write data on the W channel must follow the same order as the address transfers on the AW channel. from…
analogkp
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Xillanx Artix-7 AXI Project

I am new to AXI interface and need help understanding the flow of data from master to slave. I am trying to make a project using AXI4 with the following components using Nexys A7 board: I want to use the ADC to acquire data, and only save data that…
Shannon
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