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Questions tagged [axi]

10 questions
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VERILOG: why Xilinx AXI Slave declares all output signal as a wires and not reg?

I am reading the code for an AXI Slave provided by Xilinx (here below). I am wondering why they declare all outputs as wire and then assign them to an internal register that is modified within always blocks (see for example the S_AXI_RVALID…
leopicchio
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AXI: Restrictions on slave address spaces?

Does the AXI specification impose any restrictions on the address space of slaves? I've read the latest version of the AXI specification (chapters A1-C2, ARM IHI 0022H) and could not find anything explicit. The most I could find was the following…
MuchToLearn
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Vivado AXI attached SPI Slave

I'm trying to use the Block based design in Vivado for the first time. I am using a Spartan 7 and don't want a Microblaze in the system. My simple system was to have a SPI slave (for incoming data), an AXI interconnect, AXI interrupt controller,…
BlueTwin
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Why the AXI config registers are called GPV?

GPV stands for "Global Programmers View". It appears in Xilinx/Intel/ARM documents related to AXI interconnect, e.g., intel ARM Xilinx: section 4.4 in UG585 STM32 The function of GPV, according to the STM32 link above, is "The AXI interconnect…
bruin
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Difference between DMA and CDMA

I am studying DMA block presented in IP catalog and figure out what the best choice is. I started with AXI DMA and AXI CDMA blocks and found the following description of the difference: AXI DMA is used with streaming devices to memory mapped…
Franki Lee
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How does the master determine that the data has been completely sent from slave in AXI protocol?

The reason why a read response channel is not needed in 'read' is that if the slave doesn't send data, it can be considered that all the data has been sent. In cases where data might be interrupted, arrive out of order, or be interleaved — where the…
Carter
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What is the rationale behind enforcing WDATA ordering in AXI3?

While trying to understand the AXI protocol,I came across this: Write data on the W channel must follow the same order as the address transfers on the AW channel. from…
analogkp
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What happens when there are multiple Read requests to the same address in AXI3/4? Does RVALID assert each time?

Basically the title. I am trying to do a verification on an AXI4Lite protocol. If I try to send a read request to the same address multiple times the RVALID is not re-asserted. Correct data just remains on the RDATA channel. Sidebar question: …
user2875251
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Command interface in Axi block

could you help me to understand how the following requirement was computed: For example, a 64-bit address system requires the command word to be 104 bits wide to accommodate the wider starting address field.
Franki Lee
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Does the AXI interconnect need to subtract the offset address after decoding operation is done

The Address decoder in the AXI interconnect will based on the incoming address to determine which slave device to be targeted to. Question is does the AXI interconnect need to subtract the offset address if the targeted slave is on 2nd AXI port or…
Learner
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