Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [asynchronous]

15 questions
3
votes
1 answer

Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?

I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from iosrjournals.org that talks about communicating…
DrZ214
  • 1,029
  • 10
  • 19
2
votes
1 answer

Can I use a 3-phase driver like FNB41560 on 1- and 2-phase motors too?

I want to reduce complexity on buying many different parts and design different circuits. So I'm thinking if I can buy just FNB41560s that are well priced and simple and are capable of driving 3-phase AC motors, but using it also to drive 1- and…
bigubr
  • 69
  • 8
2
votes
1 answer

Timing Async Reset with Sync Deassert

I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my design, it seems like the best solution is to use…
FlipFlopper
  • 21
  • 2
2
votes
4 answers

Why is asynchronous data transfer only suitable for slow devices?

I have read that asynchronous data transfer is wasteful of CPU time for slow devices like keyboard or mouse. Then how is it possible that it is suitable only for slow devices like keyboard or mouse for which the data transfer speeds are…
Anshul Gupta
  • 385
  • 3
  • 12
1
vote
1 answer

Verification of asynchronous FIFO

I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings. The goal is to verify this design by using the Tb components, so no UVM at all. I should basically focus on Generator (or sequencer),…
Giuseppe Trematerra
  • 25
  • 3
1
vote
1 answer

Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right now is to realize a testbench in SV, creating all…
Giuseppe Trematerra
  • 25
  • 3
1
vote
0 answers

Initializing feedback signal in ModelSim simulation

I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit: DELAY is a delay element which I have correctly implemented using inverters. For this I have written the following…
Nacib Neme
  • 111
  • 3
0
votes
0 answers

Can a buck converter functioning in CCM have non-linear behaviour at light load currents?

I've been designing a Simulink/Simscape model of a TI buck converter launchpad (https://www.ti.com/tool/BOOSTXL-BUCKCONV) and I'm trying to have my model fit the behavior of the device. The board can be programmed to drive the buck converter in both…
Reval
  • 1
0
votes
1 answer

D Flip Flop Design on Logisim

I am trying to build a D flip-flop but I can´t get rid of those red wires. Is there a way to solve this? EDIT: I was able to fix it manually through step-by-step simulation, but I still would like to know if there is a way to avoid this problem.
dedelli_kun
  • 1
  • 2
0
votes
0 answers

Is it possible to determine the number of magnetic poles inside of an induction motors just by looking at coil windings and their respective phases?

This is in regards to a 3-phase induction motor. As far as I understand, if inside of the stator of an induction motor we have 6 windings (each 60 degrees apart geometrically) and opposite windings are of the same phase, then we get 2 magnetic Poles…
AB2
  • 11
  • 1
0
votes
2 answers

Interfacing TLC59731 with Attiny85

Has anyone had any experience communicating with a TLC59731 from an Attiny85? I'm not sure how to configure the USI to support the EasySet "protocol" described in the datasheet. I imagine I would need to configure as UART with start/stop bits…
19172281
  • 685
  • 1
  • 9
  • 24
0
votes
4 answers

How are "async/sync" and "serial/parallel" communications related?

I think "async/sync" and "serial/parallel" are orthogonal concepts. There can be 4 combinations of communication types: async serial sync serial async parallel sync parallel From the book "Serial Port Complete", I read this: In common use, the…
smwikipedia
  • 1,102
  • 2
  • 16
  • 34
0
votes
3 answers

Why does a 4-bit asynchronous counter need exactly 4 flip-flops?

We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 flip-flops.) This reduces the number of…
Manish
  • 13
  • 3
-2
votes
1 answer

STA timing closure for asynchronous FIFO

I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and write_clk are having the same clock…
kevin
  • 497
  • 8
  • 25
-10
votes
3 answers

Does this combinational lock circuit contain any memory?

Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ground. The lock is in the unlocked state when both…
Shashank V M
  • 2,279
  • 13
  • 47