Highest Voted 'artix-series-fpga' Questions - Electrical Engineering Stack Exchange

9

votes

1 answer

Is my FPGA out of routing resources?

I have a Serial-ATA Controller design working on almost any kind of Xilinx 7-series devices, except for the Artix-7 device, which gives me headaches... The pure design (SATA 6.0Gb/s, 150 MHz design clock) can be implemented on my Artix-7 200T. If I…

asked Aug 30 '16 at 23:55

Paebbels

3,897
2
18
43

5

votes

2 answers

FPGA logic threshold - distinguishing a logic 0 and 1

I'm new to FPGAs and I'm trying to determine how an FPGA determines whether to register an input as a logic 0 or 1. The FPGA I am using is the Artix 7 and I would like to connect it to a function generator giving a square wave that toggles between 0…

digital-logic fpga xilinx vivado artix-series-fpga

asked Oct 10 '22 at 23:42

PrematureCorn

558
3
17

4

votes

1 answer

Xilinx FPGA, error creating generated clock

I just got a Digilent Basys 3 board (Artix-7 FPGA) and I am trying to create a program to transmit data over the UART-USB connection. I wrote a module but when I tried to implement it I got a timing error. I have been using the standard 100 Mhz…

fpga verilog xilinx artix-series-fpga

asked Dec 24 '15 at 14:23

chasep255

523
9
23

3

votes

1 answer

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) sends out a 3-wire SPI interface to 4…

fpga spi vivado constraints artix-series-fpga

asked Nov 04 '18 at 03:26

CanisMajoris

83
1
3
9

3

votes

2 answers

Debounce on Nexys4 DDR button

I am trying to implement a simple UART transmitter, where the Nexys4 DDR board is sending ASCII characters to my PC, which I can view using Tera Term. The problem I am having is that when I press one of the buttons to send the UART data, I keep…

fpga vhdl artix-series-fpga

asked Jan 26 '18 at 19:29

nnja

31
1

3

votes

1 answer

How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you…

vhdl xilinx vivado artix-series-fpga

asked May 07 '15 at 03:49

kathir

31
1
2

2

votes

1 answer

Nexys 7 FPGA Verilog VGA signal recognized but nothing displayed

I am trying to generate images on a Samsung S22C300H monitor using the Diligent Nexys 7 board running the Xilinx Artix 7 FPGA. Even though the datasheet says the display supports 640x480, I was only able to get it to stop complaining about…

fpga verilog vga artix-series-fpga

asked Jan 03 '23 at 22:42

Luminous_

31
5

2

votes

1 answer

Is XADC synchronous in Artix 7 Series FPGA?

I was wondering if the output data of the XADC in the Basys 3 board is synchronous. That is, can I use the EOC (End of conversion) flag as a clock for some other modules and expect it to be a periodic signal? I'm in doubt because recently someone…

fpga adc synchronous artix-series-fpga

asked Jan 17 '18 at 15:37

Sebastian Araneda

123
4

2

votes

0 answers

Generating Bitstream takes very long in Vivado

This question may sound very simple but the code I wrote for a seven segment display adder with pushbuttons in VHDL takes so long to generate a bitstream. I reset and tried again several times but it has been about 4 hours now and the bitstream is…

vhdl vivado artix-series-fpga

asked Dec 04 '17 at 14:33

Ekin Alparslan

115
10

1

vote

0 answers

Artix-7 SATA implementation using LiteSATA won't initialize

I am trying to run the LiteSATA bench file provided for the Nexys Video (Artix-7 xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the bitstream to the FPGA with the following over USB…

fpga xilinx sata artix-series-fpga hdd

asked Aug 18 '23 at 16:31

md-raz

50
9

1

vote

1 answer

Is there any chance to configure DDR3L SDRAM on Digilent Arty A7 FPGA development board to Dual Channel memory?

There are 256MB DDR3L SDRAM installed on Digilent Arty A7 FPGA development board. Dual Channel memory is popular nowadays in a PC. So I was wondering if there is any chance to configure the DDR3L SDRAM on Arty A7 board to Dual Channel (or even Quad…

vivado ddr3 artix-series-fpga

asked Mar 31 '23 at 02:56

zzzhhh

21
6

1

vote

1 answer

How to get the voltage or temperature within FPGA?

I am trying to test the reliability of a circuit design on my FPGA board. (using Vivado, Artix-7 xc7a35tcsg-c board). The reliability here means the outputs of my circuit are expected to be persistent for the same input. However, many conditions and…

voltage fpga artix-series-fpga

asked Nov 13 '22 at 04:46

Li Gaoxiang

25
4

1

vote

0 answers

Daisy chaining NOR flash modules

for a project (FPGA image processing accelerator) I need to create a high bandwidth read-only memory. I settled on using Quad SPI NOR flash modules (will use them in XIP mode) but I have some concerns. First I'm not sure if I need to use buffer ICs…

spi signal-integrity flash-memories artix-series-fpga

asked Apr 12 '22 at 15:42

OM222O

282
2
11

1

vote

1 answer

Xilinx FPGA and DDR3 Memory. Confusing Impedance combinations

Currently I'm planning on doing a PCB with DDR3 memory and an Artix7 FPGA. During my research a few questions accumulated. When looking at the reference manual of the Arty7 board, I see that I have to configure DDR3 output drive strength and On-die…

fpga impedance xilinx ddr3 artix-series-fpga

asked Dec 31 '20 at 19:54

GNA

1,471
13
18

1

vote

1 answer

How to improve timing on this design using so much BlockRAM?

I'm building a small RISC FPGA CPU on an Artix-7 (Arty A7-100 (xc7a100tcsg324-1) board. It runs fine, most instructions take three clocks (non-pipelined), but due to crazy net delays, can only run at 100/50 MHz. 100 MHz for RAM which governs the…

fpga verilog xilinx artix-series-fpga

asked Dec 03 '20 at 23:29

TomServo

929
7
20

Questions tagged [artix-series-fpga]