Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [ahb]

9 questions
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1 answer

How does the cortex m0+ processor use the ahb-lite interface to fetch instruction and data?

How does the cortex m0+ processor use the ahb-lite interface to fetch instruction and data? Are instruction fetches done always using NONSEQ? How does it fetch data from memory(using burst or NONSEQ transfers) ?
Vignesh Dhamotharan
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Is it legal to design an open source AHB master?

Is it legal for open source cores to be compatible with the AMBA specification?
Revanth Kamaraj
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How to monitor the HWDATA and HRDATA in AHB-LITE on the all clock?

I'm trying to monitor the HRDATA and HWDATA on the AHB-Lite bus transfer. The monitor message should only appear when a command(Read/ Write) is issued. because this monitor connected to Scoreboard, I need the monitor signals when they are issued in…
Carter
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What causes this "stuck address" behavior in STM32 peripherals?

I recently overcame an issue while writing some startup assembly for the STM32G474, which had to do with each peripheral having a "clock enable" bit that needs enabled before the peripheral can be used. In the course of this I observed some…
Aaron Linnell
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2 answers

Clarification about Memory Address

I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, but I have two doubts mainly: My professor told…
Giuseppe Trematerra
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How to trigger CPU burst operation?

I am working on a piece of hardware design verification, which includes CPU(ARC), Design( containing AHB), and SRAM connecting to the AHB bus. I want to know if CPU can do burst write on the SRAM via AHB bus. If yes, how to implement it. Here are…
Tom Ma
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Why is data delayed by 1 clk cycle in AHB write transfer?

Here is image showing a basic write transfer: The HWDATA comes 1 clk cycle after the control signals and the address. Why is this so? What will happen if the HWDATA is put on the bus at the same time as the address and control signals and kept…
gyuunyuu
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Data during AHB Busy state

I have a question regarding the data during the BUSY state in a AHB bus. Consider the following example of an AHB master writing data onto an AHB slave: TIME: T1 T2 T3 T4 HTRANS: NSEQ BUSY SEQ …
x7ktrz
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1 answer

STM32F4 bugs in DMA, is there bug-free version?

Producer has confirmed that if there will be concurrent AHB and APB2 transfers using DMA2, then data corruption will occur (source). The bug discovery is from 2012, many years ago. Is the STM32F4 fixed now? It probably has some new revision, is…
Gortu
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