Active-HDL is an integrated FPGA design creation and simulation solution produced by Aldec, Inc.
Questions tagged [activehdl]
10 questions
8
votes
1 answer
Why does this simple VHDL pattern for a shift register not work as expected
At first glance you would expect the VHDL source code below to behave as a shift register. In that q, over time would be
"UUUU0", "UUU00", "UU000", "U0000", "00000", ....
but instead it is always U after five (or more) consecutive clock…
Jay M
- 3,753
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7
votes
2 answers
How do I build and use my own VHDL library?
I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a standard library.(or similar)
example:
library…
Hayden DeBoer
- 71
- 1
- 1
- 3
3
votes
3 answers
VHDL Error (Simple Expression Expected)
I'm new to VHDL and I'm having a problem with my code that I can't seem to fix. We're supposed to do this using either selected signal assignment or table lookup. Mine is kind of a combination of the two since we are supposed to use don't cares for…
audiFanatic
- 419
- 1
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- 14
3
votes
1 answer
How to add an internal signal to the waveform viewer in Aldec HDL for a Lattice Machxo3
I'm absolutelty no FPGA expert, but designed a device with Quartus and used Modelsim to simulate it. I was then told to modify the design and make it work with a Lattice device as they changed their mind about Altera (mainly down to Lattice devices…
DiBosco
- 1,384
- 9
- 19
2
votes
2 answers
digital logic - positive edge-triggered d flip flop triggers when input is on the decreasing edge
I have this scheme from my lecturer of digital logic. It is supposed to be an edge-triggered D type flip-flop, with a reset so there's no undefined zone at the start of the simulation of this schematic. We're using Lattice Diamond to make these…
EJay
- 23
- 2
2
votes
2 answers
VHDL Simulation bug (am I losing it??)
I've got a simulation that simply takes an address as an input and 64 clock cycles later it simply outputs it on another port. For some reason, when I register the output data, it is not delayed by a clock cycle (see waveform). Is this some crazy…
ks0ze
- 512
- 3
- 13
1
vote
1 answer
Edge detector issue
I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code is :
process (clk_i, rst_i)
begin
if (…
haster8558
- 221
- 3
- 8
0
votes
2 answers
What kind of VHDL process is this?
This is from an example that comes with VUnit inside the array_axis_vcs fifo.vhd file.
PslChecks : block is
constant dx : std_logic_vector(d'left downto 0) := (others => 'X');
constant du : std_logic_vector(d'left downto 0) := (others =>…
gyuunyuu
- 1,933
- 7
- 31
0
votes
1 answer
Delta count overflow
I'm making JKnRnS master slave flip-flop, here is my code:
library IEEE;
use IEEE.std_logic_1164.all;
entity JKnRnS is
port(
C : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
nR : in STD_LOGIC;
nS : in…
The_VFX_StyLe
- 1
- 1
-2
votes
1 answer
Can propagation delays be simulated in Active-HDL?
I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function of the hardware.
Is there a way to enable a…
Gacekky1
- 27
- 4