Electrical Engineering Stack Exchange
Electrical Engineering Stack Exchange

Questions tagged [8085]

An eight bit microprocessor made by Intel in 1976.

73 questions
44
votes
4 answers

What does edge triggered and level triggered mean?

I am studying 8085 microprocessor architecture and the terms edge triggered and level triggered confusing me really very much. Can anyone explain me it in layman's words ? While studying the interrupts of 8085 named RST 7.5, RST 6.5, RST 5.5 and…
ATR
  • 1,213
  • 2
  • 11
  • 9
17
votes
5 answers

Why in 8085 microprocessor, the clock frequency is divided by two?

Why is it that the produced clock frequency is 6.144 MHz, but internally it (8085 processor) uses only 3.072 MHz. Also what leads to the specific value of 6.144 in a clock. I found an answer at yahoo....…
loxxy
  • 173
  • 1
  • 2
  • 6
11
votes
3 answers

does 8085 CPU have an extra register within ALU?

From the 8085 CPU architecture, when ALU done calculation, the result is clocked back to accumulator A on next clock edge. But accumulator A is directly wired as ALU input, what if the clock edge didn't raise fast enough to cause A is being added…
starx
  • 161
  • 6
7
votes
3 answers

Reading/Writing a usb flash drive

I wish to expose a usb flash drive and read it as raw binary data, particularly read each byte & simultaneously writing it to another flash drive. Given that I am working with an 8085 microprocessor, & I am in a position to program it & read data…
loxxy
  • 173
  • 1
  • 6
4
votes
2 answers

What exactly is latch?

I've very less knowledge in electronics, I've read that a latch is a simple circuit that stores 1 bit of data (or state). A Latch is a circuit that has two stable states and can be used to store state information. That means it is a noun or a…
sirajalam049
  • 143
  • 1
  • 5
4
votes
4 answers

Memory mapping in the 8085 microprocessor

In the 8085 microprocessor there is 64 kb of memory available of which some are assigned to ROM while others are assigned to RAM. My question is, why is ROM always mapped to a lower region of memory map in the 8085 microprocessor?
Rahul Kumar Singh
  • 331
  • 2
  • 5
  • 8
3
votes
1 answer

How can memories be implemented efficiently with memory blocks of different sizes?

I am unsure if I am framing the question correctly, but here's what I wanted to ask. Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory. One simple way would be to use a complete 64 kB…
Vedanta Mohapatra
  • 175
  • 6
3
votes
1 answer

8085; Why RET doesn't require a 6 T-states Fetch cycle?

The CALL instruction, requires 5 machine cycles, namely, OPCODE-FETCH, MEMORY READ, MEMORY READ, MEMORY WRITE, MEMORY WRITE. The OPCODE-FETCH cycle of CALL has 6 T-states to take care of the decrements of the Stack Pointer. RET instruction…
Aravindh Vasu
  • 481
  • 4
  • 13
3
votes
4 answers

what does byte 2 and byte 3 mean?

An instruction from the instruction set of intel 8085 that is SBI data (Subtract immediate with borrow) . This instruction says "The contents of the second byte of the instruction and the contents of the CY flag are both subtracted from the…
Suhail Gupta
  • 278
  • 1
  • 5
  • 14
3
votes
2 answers

Building an Intel 8085 trainer

I'd like to build an Intel 8085 trainer for a final year project. The trainer will be used by students and will basically accept machine code entered by students, load these into RAM and run the code. Students will also be able to single-step…
SoreDakeNoKoto
  • 1,635
  • 1
  • 13
  • 22
2
votes
2 answers

Why in HL pair, H is stored after L register

Why in 8085, during LHLD and SHLD instructions L is used first while in BC and DE, B and D are used respectively?
Gowtham
  • 179
  • 2
  • 2
  • 8
2
votes
1 answer

Why does the conditional CALL instruction in the 8085 microprocessor take 2 machine cycles, when the condition is not satisfied?

When the condition gets checked in the 6th T-state itself and is found to be not satisfying, why does it need the 2nd machine cycle?
Aditya
  • 269
  • 1
  • 7
2
votes
2 answers

8085 ;JMP instruction

How exactly is JMP XXXXH; executed ? First the PC(Program counter) will contain the address where this instruction is present. In first machine cycle opcode will be fetched and PC will be incremented . Now in the second machine cycle we have to…
Urooj
  • 73
  • 1
  • 4
2
votes
1 answer

8085 ; High impedance state of lower order address/multiplexed data bus during memory read and write machine cycles

The two pictures are of memory read and write machine cycles . Could somebody please explain why in memory read cycle the lower order address / multiplexed data bus is in high impedance state at the positions I've marked with red in the timing…
Urooj
  • 73
  • 1
  • 4
2
votes
1 answer

IO mapped IO design problem

While going through the solution of the above problem i noticed something like below. Address of port A becomes 11100000. Can't get that. I am confused why it's not 01100000. Thank you!!
Surya Bhusal
  • 149
  • 1
  • 11
1
2 3 4 5