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There is an eval board for the Xilinx Zynq-7000 FPGA called the Zedboard. When you look at the board you will notice a very interesting pattern of bypass capacitors. The designer has a technical note that explains why he/she thinks this is a good way to do bypass for a board like this.

Are there any flaws in the reasoning behind this bypass capacitor scheme?

Zedboard bypass cap locations around FPGA

Disclaimer: I will not answer my own question, as I really would like other experts from this community to bring their knowledge to the table. But I may do a measurement some day to find more facts - and may blog about it + add that here.

Rolf Ostergaard
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  • In that PDF, the author describes how trace and via inductance can be an issue. The author then talks about how he measured the power supply ripple, **directly across the capacitor pins**, therefore completely failing to measure the ripple value that matters at all (the one at the pins of the Zynq, after the via and plane inductance). What? A proper way to test the decoupling would be to add test-pads on the bottom side of the PCB that expose the power delivery vias, and even that isn't ideal. – Connor Wolf Jan 23 '14 at 09:12
  • Basically, that's a giant pdf with the conclusion "Capacitors work!". – Connor Wolf Jan 23 '14 at 09:14

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He seems to be trying very hard to justify his design tradeoffs. @Conner Wolf is completely right, measurement across the capacitors is not (all) we care about. Trace/via impedance at the current ripple frequencies you see on power-pins on these high-clock-speed parts can become really considerable.

Its all a little unusual, every design has tradeoffs that need to be made and you try to chose wisely...and then verify under test of course. You don't need to write a PDF about why you needed to put x in position y because of limiting factor z.

BGA is generally a pain to route-out but I usually try to place/route clock sources first and then decoupling/power and THEN signals. My logic is that I've had issues with clocks before, but no issues yet with decoupling or signals and that I would consider optimising decoupling and power routing to be higher priority than signal routing.

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