How to assign physical pins of FPGA to Xilinx ISE Verilog modules?

Question

Recently I started learning FPGA programming. I have the " Verilog QuickStart book" and downloaded Xilinx ISE Webpack v14 and watched a number of YouTube videos. At this moment I can build my circuits and test them by the inbuilt simulator but I don't know how to assign the physical pins of the FPGA ( the I/O buffers).

For example let's assume we have a very very simple design: just an AND gate ( Module ports include IN1, IN2 and OUT). It is easy to make the circuit on the software but assume I want to assign the IC I/O pin number 7 as IN1, pin 9 as N2 and pin11 as OUT ( all I/O ports without VREF) . Nowhere in the software (as well as the book) I saw how to do this assignment.Can anyone help me on that please?

Any help appreciated in advance.

That what the "User Constraints File" (`.ucf` extension) is for. Look it up in the documentation. — Dave Tweed, Oct 30 '13 at 15:30
@DaveTweed Thanks! This guidance was really helpful. I found my answer in ISE QuickStart Guide ( Implementation section) Please add this comment as an answer that I can mark it as the correct answer (BTW, I saw your resume, please let me tell you "congratulations" for being such a super super genius person!) : http://www.xilinx.com — Aug, Oct 30 '13 at 17:35

score 6 · Accepted Answer · answered Oct 30 '13 at 16:41

Xilinx uses (user constraints file) UCF to bridge the physical pin connections to TOP signals. This file is added to a Xilinx project

the format looks like:

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;
########################################################
#8+2 LED's for indication
########################################################
NET "FPGA_LED<0>" LOC = B21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<1>" LOC = B22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<2>" LOC = C21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<3>" LOC = C22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<4>" LOC = D21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<5>" LOC = D22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<6>" LOC = E22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<7>" LOC = F21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<8>" LOC = F22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_LED<9>" LOC = G22 | IOSTANDARD = "LVCMOS33";
#######################################################
#6 FET/IGBT gate-drive FET-outputs
#######################################################
NET "FPGA_Gate1" LOC = V22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate2" LOC = W22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate3" LOC = W21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate4" LOC = Y22 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate5" LOC = Y21 | IOSTANDARD = "LVCMOS33";
NET "FPGA_Gate6" LOC = AA22 | IOSTANDARD = "LVCMOS33";

NET "CLK_40Mhz" TNM_NET = CLK_40Mhz;
TIMESPEC TS_CLK_40Mhz = PERIOD "CLK_40Mhz" 25 ns;

This is a snapshot from one of my UCF's

I checked ISE Webpack quick start quide for UCF file. Have you made this file with that? is ISE Webpack Implementation option the best software for this purpose or I should use other softwares? BTW this is a nice answer. — Aug, Oct 30 '13 at 17:23
Honestly, I rarely use any of the ISE (be it Libero for Actel FPGA's or Xilinx) for code writing. I generally use my editor of choice (gvim) and only use such packages for the final synth — , Oct 30 '13 at 19:27
UCF is just a text file, you can either use the internal editor to assign the pins or edit it yourself (what I usually do). — FarhadA, Oct 30 '13 at 20:49
You can use PlanAhead (part of ISE) to generate a "first bash pinout" UCF file — Martin Thompson, Nov 04 '13 at 13:38

score 1 · Answer 2 · answered Nov 15 '18 at 09:23

Verify your project is selected on the source window
Double-click the Floorplan Area/IO/Logic - Post Synthesis process found in the User Constraints process group.

You'll have to wait some time till a program called Plan Ahead opens.

If you don't see a tab called Package on the right then go to Window->Package. From there you should have something like a map of the pins of your FPGA selected.
On the tab "I/O Ports" you should have the ports of your project and you could either drag and drop those ports to the desired pin on the "Package" map or you could select the pin as shown in the following picture:

I hope it solved the problem. This was tested on the ISE 14.7 Virtual Appliance (running on a virtual machine on windows 10).

How to assign physical pins of FPGA to Xilinx ISE Verilog modules?

2 Answers2