Why Xilinx ISE can't get access to my custom package?

Question

I am trying to create a custom data type which I am creating in a package using Xilinx ISE 14.5. I am trying to create a generic DEMUX to switch between buses, here is the code of the generic DEMUX:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.CustomDataTypes.all;

entity GenericDEMUX is
     -- Ancho del bus de cada salida y número de salidas
     generic( busWidth              : integer := 4;
                 channelsNumber     : integer := 4
     );

    Port (  Output  : out  Matrix(channelsNumber-1 downto 0, busWidth-1 downto 0);
                Control : in     integer range 0 to channelsNumber-1
     );
end GenericDEMUX;

architecture Behavioral of GenericDEMUX is

begin


end Behavioral;

So I created a Package to contain Matrix data type:

CustomDataTypes.vhd:

package CustomDataTypes is
    type Matrix is array (natural range<>) of STD_LOGIC_VECTOR (natural range<>);

end CustomDataTypes;

When I do Check Syntax on the Generic DEMUX I get this errors:

ERROR:HDLParsers:164 - "//vboxsrv/datos/Datos/Micro UTN/FPGA/MaquinaEstados/CustomDataTypes.vhd" Line 14. parse error, unexpected NOTCONSTRAINT

ERROR:HDLParsers:3009 - "//vboxsrv/datos/Datos/Micro UTN/FPGA/MaquinaEstados/CustomDataTypes.vhd" Line 35. Package CustomDataTypes does not exist.

I don't know what parse error, unexpected NOTCONSTRAINT means but I think it could be related to Package CustomDataTypes does not exist. Here is a Screenshot of what my Libraries tab looks like, as you can see CustomDataTypes.vhd is there:

enter image description here

However I don't see it in the design tab:

enter image description here

I tried adding it but it says it already exists.

score 1 · Accepted Answer · answered Sep 30 '13 at 18:27

1

Unfortunately not until VHDL-2008 were unconstrained arrays of unconstrained elements allowed.

In other words, for pre VHDL-2008:

type Matrix is array (natural range<>) of std_logic_vector(natural range<>);

Would have to become either something like:

type Matrix_n_by_8 is array (natural range<>) of std_logic_vector(7 downto 0);

Or use 2d arrays:

type Matrix is array(natural range<>, natural range<>) of std_logic;

answered Sep 30 '13 at 18:27

apalopohapa

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Wow that worked. So `type Matrix is array (natural range<>) of std_logic_vector(natural range<>);` is only for VHDL-2008 which Xilinx ISE doesn't support? – Andres Sep 30 '13 at 18:36
PS: How can I access the array in each index because `Output <= "0000"` gives `Wrong index type for Output` – Andres Sep 30 '13 at 18:43
@Andres Correct. I'm not even sure if Vivado supports any VHDL-2008. – apalopohapa Sep 30 '13 at 18:50
1

@Andres PS: You access the 2-d array with a comma: m(0,0) <= '0'. You can define functions that make vector assignment easier. – apalopohapa Sep 30 '13 at 18:52

Why Xilinx ISE can't get access to my custom package?

1 Answers1