What is the difference between Buried Photodiode and Pinned Photodiode? I understand that the P+/N/P structure where the P+ and P layers have the same potential is the Pinned Photodiode. So what is the buried Photodiode?
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1Is this a "pinned" photodiode or a PIN (P/Intrinsic/N) photodiode? – Sep 21 '13 at 13:41
4 Answers
This is a commonly misunderstood misused set of terminologies.
First off these are not PIN Photodiodes - which stands for P - Intrinsic- N. These have large depletion regions for higher internal QE (Quantum Efficiency) and faster response. You can't make an array with this design though.
Pinning, refers to fermi-level pinning or pinning to a certain voltage level. Or also the forcing or prevention of the fermi-level/voltage from moving in energy space.
You can get surface state pinning from the dangling Si/SiO2 bonds providing trapping centers. A buried PD (Photodiode) has a shallow implant that forces the charge carriers away from these surface traps. The Si/SiO2 surface contributes to increased leakage (dark current) and noise (particularly 1/f noise from trapping/de-trapping). So confusingly a buried PD avoids pinning of the fermi-level at the surface.
A pinned PD is by necessity a buried PD, but not all buried PD's are pinned. The first Pinned PD was invented by Hagiwara at Sony and is used in ILT CCD PD's, these same PD's and the principles behind this complete transfer of charge are used in most CMOS imagers built today.
A pinned PD is designed to have the collection region deplete out when reset. AS the PD depletes it becomes disconnected from the readout circuit and if designed properly will drain all charge out of the collection region (accomplishing complete charge transfer). An interesting side effect is that the capacitance of the PD drops to effectively zero and therefore the KTC noise \$ q_n = sqrt(KTC) \$ also goes to zero. When you design the depletion of the PD to deplete at a certain voltage you are pinning that PD to that voltage. That is where the term comes from.
I've edited this Answer to acknowledge Hagiwara-san's contribution. It has long been incorrectly attributed to Teranishi and to Fossum (in CMOS image sensors)

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The first Pinned PD was not invented by Teranishi at Sony. Teranishi was not in Sony. He was in NEC.
The first Pinned PD, in the form of P+NP sensor element on Nsub structure with the N layer floating for complete charge transfer, was invented and filed in Japanese patent by Hagiwara at Sony in 1975, and was used in his FT CCD imager in 1978 with P+NPsub sensor element, in which both P+ and P are connected.
Later, Teranish at NEC disclosed his ILT CCD PD's later, Sony introduced HAD sensor, P+NPNsub photo elemnent video camera on the market. Sony now enjoing the big sensor business with the back illuminated CMOS imager with the HAD sensing element which was Hagiwara's invention.
Confusingly, HAD sensor and the pinned PD, Teranish's ITL CCD PD's, and Haiwara's P+NP transistor structure on the Nsub are all the same thing. And the VOD punch thru mode waas naturally expected by Hagiwara' original 1975 P+NPNsub photo sensing element structure patent. So who is the inventor?

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1Welcome to EE.SE! This information is interesting, but it is not a direct answer to the question at the top of the page. Would you please edit this to address the actual question? – Dave Tweed Jun 03 '18 at 14:46
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1It is important that this reply stand for context and to correct for a historical error and misreporting. One cannot understate the importance of how significant his techniques and efforts have been. Even if this doesn't align with the EE.SE . In the previous form of my answer, I was reporting on the narrative that has been promoted in the image design community. Attribution is imortant. – placeholder Aug 16 '18 at 19:20
There is no difference in Pinned Photo Diode and Buried Photo Diode.Confusingly, SONY called it by another name, SONY original HAD ( Hole Accumulation Diode ) as SONY brand name for SONY original image sensor products. They are all confusing, but they are all the same thing as Prof.Kagami in Tohoku university said so in his technical presentations. SONY made a big business of SONY HAD CCD image sensor and is now making SONY HAD CMOS image sensor with thinned die by back light illumination.
SONY image sensor business has been protected by HAGIWARA two Patents on basic Pinned Photo Diode and could win two big patent-wars agaist Fairchild and NEC.
Hagiwara filed two Japanese patents on Pinned Photo Diode in 1975, one patent (JA 1975-134985) on the P+N-PNsub junction (thyristor type) Photo Diode with vertical overflow function and another patent ( JA 1975-127647 ) on the NPNN+ junction type photo diode with back light illumination.
See for details Aiplab

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So what is the buried Photodiode?
A buried Photodiode is a PNP junction type photodiode, with the charge collecting N layer being buied in the silicon scystal. The signal charge in the buierd N storage region is to be completely transfered to the adjacent charge transfer device (CTD) which is either CCD type CTD or CMOS type CTD.
What is the difference between Buried Photodiode and Pinned Photodiode?
Pinned Photodiode is a Buried Photodiode with the surface hole accumulation P+ lyaer with the surface potential being fixed (pinned) with no surface electric field. The surface electric field is very bad generating the surface dark current, degrading very imaging quality and creating chip yield problems.
Pinned Photodiode is always a Buired Phtoodiode. But Buried Photodiode is not by necessity Pinned Photodiode. Hagiwara at SONY invented P+NPNsub junction type Pinned Photodiode in his Japanese 1975-134985 patent with (1) very high blue sensitivity, (2) pinned surface P+ hole accumulation layer with no surface dark current, (3)complete charge transfer of the buried N layer to the adjacent charge transfer device (CTD) and (4) Vertical Ovefleo Drain Fucntion (VOD). SONY HAD is PPD + VOD. Hagiwara invented in 1975 the Buied Photodiode, Pinned Photodiode and Hole Accumulation Diode (HAD).
I understand that the P+/N/P structure where the P+ and P layers have the same potential is the Pinned Photodiode.
Hagiwara at SONY reported in his SSDM 1978 paper the P+NP juntion type Pinned Phtoodiode (PPD) where the P+ and P layers have the same potential. SONY used this PPD in Frame Trandfer CCD image sensor in SSDM1978 paper. NEC used the PPD in interline transfer CCD in IEDM1982 paper, and named Buried Photodiode while Kodak used also this PPD in interline transfer CCD in IEDM1984 paper and named this P+PN structure as Pinned Photodiode. Sony developed the P+NPwellNsub structure and used it in interline transfer CCD and named this PPD + VOD structure the SONY Hole Accumulation Diode (HAD).
PPD has the pinned surface potentail as well as the pinned emopty potential well of the complete charge transfer operation resulting the no image lag picture quality for fast action pictures. Hagiwara invented Buried Photodiode, Pinned Photodiode and SONY Hole Accumulation Diode (HAD). The evidence are give in Japanese 1975-127647 and 1975-134985 patents and Hagiwara SSDM1978 paper on the P+NP PPD used in Frame Trandfer CCD image sensor.

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