J-K Flip Flop Output

Question

For a J-K Flip Flop, once we have J&K=1, now when the CLK Goes high, so Output goes high on the falling edge, but when does the OUTPUT Goes back to LOW?

Are you asking about JK flip-flop or JK edge-triggered-flip-flop? There is difference between these terms. Maybe this post will be helpful to you: http://electronics.stackexchange.com/questions/74986/edge-triggering-seems-to-me-leaving-every-circuit-in-an-inconsistent-state/74991#74991 — Vasiliy, Sep 11 '13 at 06:21

score 1 · Answer 1 · answered Sep 11 '13 at 00:06

1

On the next falling edge, assuming both inputs are still high. The synchronous inputs (J and K) are synchronized with the clock.

answered Sep 11 '13 at 00:06

Ignacio Vazquez-Abrams

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score 0 · Answer 2 · answered Oct 11 '13 at 04:09

When Both Inputs of JK FlipFlop are High, It goes in Toggle Mode i.e. Q = Q'.

So, Assuming it's Falling Edge Triggered flipflop, On Next Falling Edge, Output will be LOW again. And On next Falling edge, it will be HIGH again and so on...

Wikipedia article has this table and timing diagram.

J-K Flip Flop Output

2 Answers2