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I was informed on this forum that edge triggering could be a solution for multiple propagation in a circuit with feedback (the output wired back to the input).

But to me edge triggering seems to leave a circuit in a completely inconsistent state. Look at this one (one-element JK flip flop ripple counter).

Let the clock input be edge-triggering signal and look at the first NAND field at J when all inputs at J are high but the clock. At the moment the clock gets high the propagation starts. The edge lasts for a nanosecond so it will probably end before the value propagates through the NAND. Anyway, a nanosecond-long low signal will travel through the output of the first NAND, preceded and followed by long intervals of high signal. That composition will get to the the second upper NAND and the NAND will change values accordingly, further branch-wired to another NAND plus an input, and it all looks like a great example of an inconsistent state of a circuit to me - who knows what is going to happen there?

I don't get properly something about edge triggering. What is that? Thank you for the time!

Срба
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  • It seems that I mislead you in the explanation by attaching an image of a level-triggered circuit. I am confused with edge triggering only and I chose a feedback circuit only to illustrate what mambo-jumbo would happen if instead of clock signal it was the output of an edge-triggered pulse detector.It looks to me that the first circuit gate output gets changed only for a nanosecond when it's a rising edge,then immediately reverts to the output as the edge-indicating signal is 0.Then the nanosecond signal change travels to the second gate,modifies its output for a nanosecond too,and the second – Срба Jul 06 '13 at 16:55
  • gate output spreads out to the input and the third gate simultaneously and that's where mambo-jumbo begins - the nanosecond signal modification enters circuit again, in the same time the third gate output travels for the second input...Who could know which signal gets to which target first and can predict the collisions?Looks very inconsistent.I will have to study the master-slave flip flops that @VasiliyZukanov and others attached in their great answers,since I am not familiar with those,but the circuits using pulse-detector edge-triggered signals still seem dysfunctional to me. – Срба Jul 06 '13 at 17:04

4 Answers4

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It is difficult to understand what are you asking about without some sort of timing diagram.

However, I'll try to guess what your issue is:

There is broad interchangeable misuse of terms "gated latch", "flip flop" and "edge-triggered flip-flop". The schematic you provided is not JK edge-triggered flip-flop, but JK gated latch, commonly referred as JK flip-flop.

As opposed to edge triggered flip-flops which change state only on the rising edge of the clock signal, gated latches can change state during the whole positive phase of the clock signal. This means that if either J or K inputs change while the clock is high, the output of gated latch may change too (which is not true for edge-triggered flip-flops).

However, if J and K inputs are held constant during a positive phase of the clock, the output of JK gated latch will settle to a known value (with one exception described below), which may be derived from the values of J, K and Q at the rising edge of the clock. NOTE: the fact that we are looking at the values of the signals at the rising edge does not imply that this JK gated-latch is edge triggered, because we assumed that the inputs will not change during positive phase of the clock!!!

Now, to your question: it seems that you can't grasp how exactly the output may settle to a known (and deterministic) value, taking into account the two feedback loops present. Well, the only way you can convince yourself is to assume some initial conditions on the output and trace what happens for each possible combination of inputs (except J=1,K=1).

The following two points will make your life easier:

  1. While the implementation with NAND gates is the most area effective, for the purpose of understanding the concepts it is best to investigate this (functionally equivalent) circuit: Implementation of JK gated latch with AND and NOR gates
  2. Note that when the clock is high, the outputs of AND gates will be determined by the values of J and K inputs, and the value of Q. It means that you may erase the clock signal from the diagram in order to understand what's going on during the positive phase of the clock.

EDIT: So what about J=1, K=1 case? Well, in this case JK gated-latch becomes a multivariator (I hope the term is correct) - its outputs will be changing periodically during the positive phase of the clock. In logic circuits this combination of inputs is illegal, therefore the usual practice is to tie them together in the following manner (which is called D gated-latch):

enter image description here

Note that there are no need in feedback in this circuit, because the outputs are completely determined by the value of D input.

In order to construct edge-triggered JK flip-flop, one can put two JK gated-latches in series in the following way (there are also other configurations). Note that the feedback paths are from the output of the second gated latch to the input of first:

JK edge-triggered flip-flop

In this configuration there are no more restriction on J=1, K=1 input combination - this combination of inputs means "toggle the output". The so-called T edge-triggered flip-flop is usually derived from the above JK edge-triggered flip-flop by tying J and K inputs together.

Vasiliy
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  • Vasiliy, is this a diagram of an edge or level triggered circuit? I see pulse detector circuit that catches the edge but I see the high level lasts for a half of cycle on your diagram? – Срба Jul 05 '13 at 14:56
  • Sorry for confusion. I meant to put the basic JK gated-latch there. Fixed it now, and added the diagram of JK edge-triggered flip-flop – Vasiliy Jul 05 '13 at 15:18
  • And I forgot very important detail: J=1, K=1 (which is "toggle" combination for JK edge-triggered flip-flop) is illegal combination for JK gated-latch, because it becomes a multivibrator - its outputs will be changing all the time! – Vasiliy Jul 05 '13 at 15:29
  • The output of a JK flip flop can only change once for each falling edge of the trigger input. There there a minimum required pulse width for reliable operation, but pulses can be as wide as desired provided they exceed that minimum. The only problematical types of clock inputs are runt pulses, click pulses which occur too close to transitions on the JK inputs, or slowly-changing clock signals which hover too long near the threshold. – supercat Jul 05 '13 at 16:51
  • @supercat, I believe that you're talking about JK edge-triggered flip-flops, and not about JK gated latches. I tried to explain the difference in my answer - if you still can't see the difference after reading it, well, I failed. – Vasiliy Jul 06 '13 at 06:58
  • @VasiliyZukanov: I have never heard of a JK gated latch. I have heard of RS gated latches, but they make no pretext of toggling if both inputs are high. The RS gated latches I'm familiar will bet set when S is high, R is low, and enable is active, and will be reset when R is high, S is low, and enable is active. At all other times they hold their state. – supercat Jul 06 '13 at 17:58
  • @supercat, the first picture in my answer is JK gated latch. Try to see what happens when J,K=1 and the clock is high - it becomes a multivibrator. – Vasiliy Sep 11 '13 at 06:19
  • @VasiliyZukanov: In what circumstances would the circuit with the feedback terms to the first AND gates be more useful than a circuit with those terms omitted? Such a circuit practically yearns to find itself in a metastable state, *even if J and K aren't driven high simultaneously.* For example, assume Q starts high, and K and Clk are driven high. As the output of the top AND goes high, the output of the NOR may start to go low. That could in turn cause the output of the AND to go low before the lower NOR goes high. – supercat Sep 11 '13 at 17:39
  • @VasiliyZukanov: While I can see that adding the feedback terms turns some defined behaviors into ambiguous or metastable behaviors, I don't see any case in which the circuit you call a JK latch has any *defined* behavior which differs from that of a gated RS latch--at least not in the absence of specified propagation-delay constraints. – supercat Sep 11 '13 at 17:41
  • @supercat, I just explained the terminology. The question whether JK gated latch is used at all is completely different one (you're welcome to add it to the forum). As long as you understand the difference between JK gated latch and JK edge-triggered flip-flop - this answer achieved its purpose. – Vasiliy Sep 12 '13 at 06:46
  • @VasiliyZukanov: Okay, I re-examined the original question; it seems it presupposes the use of the circuit somewhat like you describe (though with NAND gates), and so your answer presupposes that the circuit could be suitable for some purpose. The transform could affect propagation behaviors, and thus doesn't seem safe. I would suggest that if one wants a latch which can be toggled via pulse, it should be drawn with separate early-stage gates for the "toggle" case and the other cases, since there is otherwise no input stimulus which would be guaranteed to clear metastability in timely fashion. – supercat Sep 12 '13 at 15:32
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The basic J K flip flop suffers from a timing problem called race where the trigger pulse is too long and the the circuit sends back confusing signals which is what I think you are describing.

To get around this the trigger or clock pulse has to be kept very short so that it returns to a '0' before the change in the output can be propagated back to the input gates.

enter image description here

The J-K flip flop operation can be improved by adding a second R-S flip flop and is known as a master-slave J-K.

enter image description here

At the rising edge of the clock signal, the J and K input values are propagated to and stored in the master flipflop, while the slave flipflop (which is controlled by the inverted clock) remains unchanged. On the falling edge of the clock signal, the output values of the master flip flops are propagated to and stored in the slave flipflop, which in turn drives the flipflop Q and Not Q outputs.

JIm Dearden
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    the only combination of inputs for which JK flip-flop suffer from "race-around" condition is J=1, K=1. This should be mentioned. – Vasiliy Jul 06 '13 at 07:17
  • @VasiliyZukanov Quite correct - any other combination of J K values will produce a S -R latch type circuit with 0 0 being the 'no change' value. Only with J K as 1 1 will the circuit act as a Toggle type divider with the "ace-around" condition. (+1) from me – JIm Dearden Jul 06 '13 at 10:23
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Most real circuits use D flip-flops, which have two relevant constraints: a "setup" time during which the signal must be constant before the edge arrives, and a "hold" time after the edge during which it does not arrive.

The design is then simulated and adjusted so that each signal arrives within the setup time and not earlier than the hold time. Yes, you can insert a delay element (e.g. pair of inverters) to meet the hold constraints.

Some designs of D flop can have a zero hold time, so that as soon as the edge arrives their input is locked in and stable.

("Edge lasts for a nanosecond": that feels rather high to me!)

pjc50
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Master-Slave flipflops, synchronous clocked switching and the like exist for a reason. Edge triggering can be designed to be statistically highly reliable in practice, but the hazards and shortcomings are well known. Edge triggering and asynchronous operation are usually cheaper and easier to design overall. As with most of life it is a tradeoff between many factors and can be made to work "entirely well enough" in many cases. You'll be less likely to find it in life support & fire control systems and, one hopes, satellite launchers.

Russell McMahon
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  • Then most of the circuits used where accuracy is critical are level-triggered circuits and in the case of an feedback circuit the designers have to make sure that the propagation will last longer the high-clock-level interval, but shorter the the whole clock cycle in order to prevent multiple propagation in the high-clock-signal interval of the cycle? By adding some components that should only slower the propagation? – Срба Jul 05 '13 at 11:57
  • I hav erealised that this answer is less good than could be. No time at present to tidy it - I'll be back. The main villain is asynchronous versus synchronous clocking / propogation. States are latched in system wide everywhere on a clock edge so no ripple carry and "race hazards" can occur . – Russell McMahon Jul 06 '13 at 02:50