Indexed Vector Part select operator +: usage in verilog

Question

I am using Indexed Vector Part Select in a Verilog test case and i am very confused with this.

when we have described

input [415:0] PQR_A;
output [63:0] ABC;

then is it valid

assign PLA=PQR_A[44*8 +: 64]

because i think in this way the bits will be from 352 to (352+ 64) i.e. 416, which is not valid

I know this is quite silly to ask that what is [0:7], it means 0,1,2,3,4,5,6,7 i.e. 8 bits.

score 2 · Accepted Answer · answered Jun 28 '13 at 13:39

2

Indexed vector select w[x +: y] has width y. The equivalent regular select is w[x : (x+y-1)] .

answered Jun 28 '13 at 13:39

shuckc

Code has little endian notation, so first answer is right – Prash N Dec 24 '15 at 14:15

score 1 · Answer 2 · answered Feb 08 '21 at 12:41

1

one line explanation of that is :

w[x +: y] == w[(x+y-1) : x ]

answered Feb 08 '21 at 12:41

robert

score 0 · Answer 3 · edited Aug 08 '14 at 21:05

0

I think it should be like this: w[x +: y] == w[(x+y-1) : x ]

For example:

a_vect[ 0 +: 8] == a_vect[ 7 : 0]

edited Aug 08 '14 at 21:05

Ricardo

answered Aug 08 '14 at 20:45

Charles

1

Can you elaborate why your answer has the order flipped from the already accepted answer? – Adam Head Aug 08 '14 at 21:01

3 Answers3