Difference between If-else and Case statement in VHDL

Question

I want to understand how different constructs in VHDL code are synthesized in RTL.

Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL circuit by the synthesis tool ?
Do consider the case of multiple nested if-else and mixing case-statements with if-else construct inside a process.
Also when to use which construct ?

PS: I have seen a related question "Multiple if statements in process in vhdl" but that doesn't answer my question in anyway.

I can't comment on how the physical gates would be configured, but in most compilers that emit x86 assembly an if-else usually exists as a single check with a conditional jump (e.g. jg, jl, jz, jnz, etc.), whereas switch organises the cases in numeric order and does iterative `dec` / `jz` instructions, which is much more efficient. Perhaps a similar optimisation is applied here. — Polynomial, Jun 19 '13 at 21:34
@Polynomial The behavior of If-else and case are significantly different in hardware languages compared to your typical linear programming. Op-code optimizations are not very relevant since the HDL statement executes "instantly". — W5VO, Jun 20 '13 at 04:39

score 16 · Accepted Answer · answered Jun 20 '13 at 13:44

16

Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL circuit by the synthesis tool ?

The if-elsif-else construct infers a priority routing network:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

This corresponds to

if bool_expr_1 then
    sig <= val_expr_1;
elsif bool_expr_2 then
    sig <= val_expr_2;
elsif bool_expr_3 then
    sig <= val_expr_3;
else
    sig <= val_expr_4;
end if;

The case construct, on the other hand, infers a big ol' mux:

enter image description here

This corresponds to

case case_expr is
  when c0 =>
    sig <= val_expr_0;
  when c1 =>
    sig <= val_expr_1;
  when c2 =>
    sig <= val_expr_2;
      ...
  when others =>
    sig <= val_expr_N;
end case;

Obviously these are very simplified designs with only one value expression, resulting in one output.

Do consider the case of multiple nested if-else and mixing case-statements with if-else construct inside a process.

Per the above, you can see how they would nest/mix.

Also when to use which construct ?

Since if-else infers priority, it should be used when more than one input condition could occur. Using case, one the other hand, is appropriate when the inputs are mutually exclusive.

answered Jun 20 '13 at 13:44

Angelo Stavrow

376
1
3

I understand that case statment works only for single input condition and if-else can work for multiple input conditions. But both constructs essentially generate muxes(in absence of clk). Isn't it possible that logic synthesis may optimize single-input if-else to a single big mux instead of chain of muxes ? Also, what is a priority routing network ...isn't this simply chain of muxes instead of 1 big mux ? – nurabha Jun 20 '13 at 14:19
Additionally, when we have a process sensitive to a clock, if-else can generate sequential elements such as registers, latches etc. Can a case statement also generate sequential logic ? – nurabha Jun 20 '13 at 14:20
Yes, a priority routing network is exactly that - a chain of muxes. The nature of the `if-else` construct, however, is where that chain arises. The first condition *must* fail for the second condition to be tested. This is not the case for, er, the `case` construct, and this is why an `if-else` statement could not be synthesized as a single large mux. – Angelo Stavrow Jun 20 '13 at 14:42
1

And yes, a `case` statement can generate sequential logic as well. I found ["Real World VHDL"](http://userweb.eng.gla.ac.uk/scott.roy/DCD3/03_VHDL_Real%20World.pdf), a series of lecture slides from the University of Glasgow, which may be helpful to you. – Angelo Stavrow Jun 20 '13 at 14:45
This is a good reference. – nurabha Jun 20 '13 at 22:50
Angelo Stavrow: Does this mean, that the case-example has less delay from input to output than the if/else-case? – Stephan Møller Apr 27 '20 at 21:47

score 5 · Answer 2 · edited May 23 '17 at 12:40

In this old blog post, the author wrote and synthesized two functionally equivalent versions of VHDL code. One using if-else, the other using case. The result:

I synthesized this code and got the exact results.Even the RTL schematic was exactly same for both of the programs.

And his conclusion:

This shows that 'case' and 'if...elsif...else' statements are both equally efficient.But if you want to write a clear code,then you better use 'case'.'case' is very useful when the output depends upon a large number of conditions.But if the number of conditions are very small(2 or 3) then you can use 'if..elseif..else'.

There are also dozens of posts on this subject on Stack Overflow for every conceivable language. The conclusion is generally the same, that there is no difference performance-wise. Occasionally, if there is a large number of cases, a compiler may be smart enough to create a look-up table which would yield slightly better performance.

A VHDL synthesizer may be able to do the something similar. But you would still need a large number of cases in which case (pun intended) you would probably want to use a case statement anyways as it provides better readability where there is a large number of options.

Difference between If-else and Case statement in VHDL

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