std_logic_vector to unsigned conversion throwing incompatible error

Question

Below is a VHDL code of a even/odd parity generator for a bus of given width.

library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all;
use ieee.math_real.all;

entity paritygen is
    generic( WIDTH : positive := 8 );                          -- Bus width
    port   ( abus  : in std_logic_vector( WIDTH-1 downto 0 ); -- n-bit Bus
             even  : out std_logic;                           -- Even parity bit
             odd   : out std_logic );                         -- Odd parity bit 
end paritygen;

architecture behavioral of paritygen is
begin    
    process( abus )
        variable sum  : unsigned( natural( ceil( log2( real( WIDTH + 1 ) ) ) ) - 1 downto 0 );
        variable remdr: unsigned( natural( ceil( log2( real( WIDTH + 1 ) ) ) ) - 1 downto 0 );
    begin
        sum   := (others => '0');
        remdr := (others => '0'); 

        for i in abus'range loop
           sum := sum + unsigned( abus(i) );
        end loop;

        remdr := sum MOD 2;

        if ( remdr = 0 ) then
            even <= '1';
        else
            even <= '0';
        end if;
        odd  <= not even;
    end process;    
end behavioral;

When I compile the code in Synopsys Synplify Pro I get an error on the following line:

sum := sum + unsigned( abus(i) );
error: @CD715: Cast of incompatible types

In this line, I am calculating a running sum (of unsigned type) of all bit-lines of the bus. As bus is of type std_logic_vector, I am casting it to unsigned type before using add operator to calculate sum.

The error vanishes if I remove the explicit casting. I am confused as to why this is incompatible casting because as I know std_logic_vector should be casted explicitly to unsigned type using unsigned keyword. Can anyone tell me what is wrong in my vhdl code ?

have you tried using `... + unsigned( abus(i downto i) )`. I did not check this with my synthesis tool, but is is possible that `abus(i)` returns a value of type `std_logic` and not `std_logic_vector`. It is however strange that the code synthesizes fine with no type cast at all... — andrsmllr, Jun 17 '13 at 19:10
@damage: I think I too think that the problem is with return value of abus(i) of type std_logic. I will try with the syntax you mentioned. Thanks — nurabha, Jun 17 '13 at 21:56

Marc · Answer 1 · 2013-06-20T14:58:06.017

1

Problem here is that abus(i) is of type std_logic and no vector. Inserting a '0' helps to create a vector that can be casted to unsigned:

sum := sum + unsigned( '0' & abus(i) );

Here's a helpful numeric_std cheat sheet: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

edited Jun 20 '13 at 14:58

answered Jun 20 '13 at 13:57

Marc

136
6

score 0 · Answer 2 · answered Jun 20 '13 at 03:03

0

Not sure off the top of my head, but don't you need to throw to_integer() around it? E.g.,

sum := sum + to_integer(unsigned( abus(i) ));

answered Jun 20 '13 at 03:03

JustJeff

19,163
3
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std_logic_vector to unsigned conversion throwing incompatible error

2 Answers2