It seems that GaN has higher Rds(on) than SiC.
The lowest Rds(on) that I found for a 650 V GaN is 25 mΩ @ 25°C. SiC has even lower resistance @ 1200 V like 16 mΩ @ 25°C.
Does anyone know the physical reason? Does it mean that GaN can provide better efficieny due to its better switching parameter? Obviously it means that GaN at low swicthing frequency is worse than SiC.
As some comments have already pointed out, Rds(on) is just one parameter among others. It's similar to how you'd deal with reducing resistance in any circuit—by adding more MOSFETs in parallel.
Manufacturers sometimes go for a strategy where they increase the size of the transistor die to lower its resistance. But there's a catch. The larger size also leads to higher capacitance, making it a bit harder to control the transistor effectively.
Now, for a more meaningful comparison, you could consider the product of Qds and Rds(on), along with some other factors like Figures of Merit. This gives you a better overall picture since it takes into account the actual physical properties of the MOSFETs.
Anyway there are some differences between GaN and SiC and it's theoretical limits but the real characteristics of the transistors can vary a lot.
Source of the picture: IEMN
The largest (lowest Rds(on), highest Qg, etc.) devices available at a distributor, or from manufacturers, is literally just what they happen to have on hand, or on offer, and at best reflects market trends; there's little if anything fundamental about the chips themselves.
Another possibility you might not've considered: yield. Particularly among newer semiconductors, defect rate or process yield may be poor. As I recall, SiC wafers have a certain density of screw defects, the most pernicious kind in the material; if a transistor happens to fall on a location with too many of these, it may be rejected. There is thus pressure to reduce device size to maximize yield. As defects get ironed out of the wafer-production process, maximum economical chip size will likewise grow.
I don't know the stats for modern GaN processes (usually epitaxial over buffer layers over Si), but there may be similar size or yield limitations due to the behavior of that process.
For reference, the yield limit for standard Si is around 1-2cm, where the limitation is not so much process yield (after the better part of a century's collective industry experience, they're very good at working with Si), but packaging limitations: the chip can't be bonded to a reasonable substrate (like Cu) without enduring excessive stress due to thermal expansion.
As far as I know, the chips in SiC and GaN devices are extraordinarily small, in comparison to Si devices of similar ratings; their performance really is just that good. (It also shows off SiC's great thermal conductivity, that similar power ratings in a TO-247 can be had from a die a fraction of the size!)
There are still other limitations. There may not be much demand -- or purpose -- for very large, very fast devices, because package strays dominate their performance. SiC are widely available in traditional, high-inductance packages like TO-247, or brick modules; GaN is so fast, it's preposterous to place in such a package, and fortunately manufacturers have been wise enough to introduce them widely in DFN style packages. The wide, short and low connections minimize transmission line impedance and length, minimizing losses (let alone outright destruction!) due to strays. (They serve much the same purpose as traditional stripline RF transistor packages, but plastic DFNs are much cheaper than gold-plated metal and ceramic.)
In other words: for say a 10kW GaN converter, not only would it be impossible to try and use a 10mΩ chip at the ~ns risetime these devices are capable of, it's more efficient anyway to use many in parallel -- most likely not directly in parallel, but rather as independent channels working together such as a phase-interleave scheme. This keeps the switching impedance (roughly speaking, the Vpk / Ipk at the switch) much more manageable. (The effect of stray inductance and capacitance is relative to the switching impedance: consider Zstray = √(L/C) for loop inductance L and drain capacitance C. Generally we want Zstray less than Zsw, and snubbing is required if Zstray is greater and t_stray = π √(LC)/2 is comparable to or greater than t_r.)
GaN also isn't yet widely available in higher voltages, whereas SiC has been steadily delivering parts in 1200 and 1700V ratings -- suitable for 100s of kW applications on 400/480V mains (industrial, solar, etc.) and EVs. With more voltage headroom, more package inductance is tolerable, permitting much higher power levels per device/module.
Note that SiC modules may consist of multiple dies in parallel, so the device ratings again don't say anything about material capability or process yield; just that these are marketable solutions.
