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Good day,

I am currently working on a RISCV32 core for a personal project in order to learn FPGA developpement.

I have fully implemented all the base instruction set instructions and each of them is executed in a single clock cycle, with some clever state machines here and there.

I have now decided that I should move to the next step which is making my CPU pipelined and came to a stall. It is not the concept and the idea that confuses me, but what does however is the way I should go about implementing it.

Since it is a 5 stage pipeline, and I have all my instructions execute in one clock cycle, will I have to extend the time it takes to execute each instruction, expanding to 5 clock cycles, or 2,5? I know that the idea is to increase the throughput, and not the speed of each individual instruction, just want to make ure that I understand that this is the way to go.

For those interested to have a look, here is the github: https://github.com/VladimirMeshcheriakov/Le-FauxrjePGA-CPU (Please dont take the README in account, it is an inside joke)

Thanks in advance!

toolic
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Vladouch
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    "*just want to make ure that I understand that this is the way to go*": It sounds to me as though you are asking "why pipeline?" Yes, you do write that "*the idea is to increase the throughput*" -- and that's broadly correct (consistent with cache hit/miss and memory cycle times.) So what are you really asking about? Whether to use 5 or 6 or 4 or 9 stages? Or to do it, at all, given that you have something already working without pipelining? I guess I'm confused about what you really are struggling to gather up and/or need to hear. – periblepsis Aug 25 '23 at 05:44
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    I thought I was being very clear, my question is how to switch to a pipelined implementation knowing that currently eah instruction executes in one clock cycle. Is it possible to keep it that way and make the CPU pipelined? Or do I have to increase the clock cycles per instruction? – Vladouch Aug 25 '23 at 10:05
  • Well, you can kinda do whatever you want! You're the chip designer. You need to ask yourself - what are you trying to optimise for? Raw performance? Performance per watt? Performance per gate count? The optimal pipeline design will be heavily influence by these requirements. You can even take it a step further and look at the type of processor loads you want to design for (e.g. DSP). Pipelines are an optimisation, but there is always a tradeoff, so the most important thing is to define what you're trying to achieve in the first place. – Jon Aug 25 '23 at 14:34
  • @Vladouch You aren't communicating clearly to me. That much is certain. The reason for pipelining will be to increase the clock frequency, assuming that can be supported by external resources. Anyway, you aren't connecting with me. Perhaps others are smarter and can read your mind better. I'll leave it to them. – periblepsis Aug 25 '23 at 16:05
  • You’re asking a high level design question but give us the low level implementation. How do we get a picture of your high level design without reverse engineering your code? Got me beat how you would execute an instruction in one clock without pipelining and using state machines? The state machines need to be clocked, so if you execute one machine instruction per clock, what is the state machine doing? – Kartman Aug 26 '23 at 02:19

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