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So I've recently discovered that when a crystal oscillator says "20pF", it does not mean "use 20pF caps". (Despite that the design I made under that assumption appears to work.) However, I see two different equations used in different places. Assume L = load capacitance, C = the value of one of the paired capacitors, S = stray capacitance.

  1. L = (C/2)+S
    Citation: some TI microcontroller datasheet, see how to select capacitor for a crystal oscillator
    Citation: RP2040 hardware design pdf, section 2.3, https://datasheets.raspberrypi.com/rp2040/hardware-design-with-rp2040.pdf

  2. L = (C+S)/2
    Citation: this TI info video, around 6:10, https://www.ti.com/video/6313368697112
    Citation: another misc chip datasheet, see Stray capacitance for crystals

So what's up, here? The net difference is S/2, which, if you cared about S in the first place, seems non-negligible.

Erhannis
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    Over many years, crystal size has shrunk, which also shrinks its internal capacitance. While oscillator size has also shrunk some, it hasn't kept pace with shrinking crystals. So stray capacitance associated with oscillator circuits has become more important. Note too that modern oscillators tend to run at low power - those tiny crystals can't take much. – glen_geek Aug 10 '23 at 16:07

2 Answers2

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For SMT crystals with 0603 capacitors or smaller, S is in the order of 1-2 pF, so S vs S/2 is less than your measurement error and negligible. As long as you understand that there is stray capacitance, you can adjust for it or calibrate it our.

Lior Bilia
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Clearly, the crystal only sees whatever total it does; if Cstray is from one terminal to GND, then both strays act in series, and Cs/2 must be used.

The RP2040 doc doesn't specify how their Cs is placed/measured. Indeed, given the use -- they add 5pF straight to the total -- we can assume they mean 10pF from each side to GND. Which, maybe that's a little on the high side, maybe it's about right for the pin capacitance, who knows.

There is one catch: note they're using a series resistor to set drive level (presumably the output pin is a full-level logic out; offhand, I don't see if this is defined anywhere), so that pin's capacitance does not participate, it's a low impedance to begin with (i.e. normal-strength logic drive is on the order of 40-70 ohms) and the resistor swamps its impedance. Cs on the XOUT side, then, is only the traces in the area -- which may be very small indeed, under 1pF say.

And, if the capacitances aren't symmetric, then a slightly different formula must be used -- take the sum capacitance on each side, and use the "parallel" formula (by which I mean: the values of capacitors connected in series uses the parallel-resistor formula) to get the total. (That is, Cser = (Ca Cb) / (Ca + Cb). When Ca = Cb, this reduces to a factor of 1/2.)


As you've noticed, these things are loose enough that they tend to Just Work(TM), even when things are a bit out. The main downsides are: potentially unreliable oscillation (over temperature range and manufacturing spread), and frequency slightly off (e.g. you might want a trimmer on a very accurate RTC; or better(?) yet, fix up the timing in software).

Ideally, one evaluates a crystal oscillator by obtaining a representative sample of the manufacturing range of the device in question (close to process min/max; the manufacturer may be able to provide samples for this purpose), and measuring the crystal power level for both manufacturing and temperature extremes. Include power-up conditions (not just leaving it running while varying temperature) to be sure it's able to start up. And anything else that might contribute, like variation of your supply voltage, other heat sources in your system, etc.

Most of the time, this level of scrutiny isn't worth it, and product testing during/after assembly, or field reports of marginal operation, provide a loose indication of stability.

Tim Williams
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  • So which equation they use basically depends on which Cs they mean? I guess that resolves the conflict, if still kinda annoying. So, for most SMD purposes, C = 2L-5pF would probably work, yeah? And plus or minus a few pF for cap availability. – Erhannis Aug 10 '23 at 15:37
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    Something like that, yeah. It's not like it's hard to look at: identify pin types, find capacitance (sometimes it's in the datasheets, sometimes appnotes, sometimes not at all in which case a fixed assumption is as good as anything), estimate stray from PCB layout (trace + pad area, more or less), put it together and there's your answer. – Tim Williams Aug 10 '23 at 15:39
  • Yeah, but I don't know the effect of *half* of those things, and it's yet another weird gotcha bundled into electronics. I'd like to file a complaint with physics and with electronics engineers: your systems are needlessly complex and fiddly, please tone it down. ;P Thanks for the help – Erhannis Aug 10 '23 at 15:48