Active pull-down in LSTTL totem-pole output

Question

The lower totem-pole transistor of a LSTTL IC frequently has an active pull-down from base to emitter (ground). Here is an example from TI's SN74LS93 datasheet.

I was curious how this active pull down affected the circuit, so I implemented a similar circuit using CircuitLab. Since CircuitLab does not appear to have Schottky Transistors implemented, I used standard NPNs with Schottky Baker Clamps. I used values for the resistors found at this webpage.

^{simulate this circuit – Schematic created using CircuitLab}

I ran a DC sweep on the input current, monitoring the voltage at the base of the output transistor.

As easily seen, the voltage at the base of the output transistor rises very rapidly to the forward voltage of a PN junction, even with uAs of current.

Then I ran the same test without the active pull-down circuit.

^{simulate this circuit}

However, I was unable to discern any significant difference between the two results.

By the way, I tested to much higher levels of current, and the results of the two tests continued to match quite closely. I understand that the effect of \$V_{BE}\$ on \$I_C\$ is exponential, so even small variations in voltage might be significant, so perhaps the means I used to test the two circuits is not sensitive to show an effect by the pull-down, but at this point I wonder what is the purpose of the active pull-down.

For purely resistive base-to-emitter pull-downs, I understand that they prevent the base of the transistor from turning on until the supplied current is sufficiently high. However, in this case, the voltage at the base rises to a diode drop with very little supplied current.

My questions are:

• Does the purpose of the active pull-down have something to do with performance / switching speed?

• Does the purpose of the active pull-down have something to do with implementing low value resistors in integrated circuits?

• Is there an easy way to implement a more sensitive test in CircuitLab that demonstrates a significant behavioral effect of the active pull-down circuit? (For example, is there a way to sweep two current sources at the same time, and in sync with each other?)

• Is the way I am modeling Schottky Transistors too far from reality?

Answer 1

tl;dr: Q1 is a pull-down, which works a bit faster / more efficient than a resistor.

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The difference is not in DC; a pull-down resistor would do just as well to ensure Vbe turn-off. (Quite a large resistor at that, for DC purposes -- only needing to overcome leakage.)

The critical thing to understand about families after 7400 (and themselves to some extent) is the improvements, in both reduced current consumption (except some extremely fast families) and speed. 74LS being on the side of, similar speed, but 1/10th (I think?) current consumption -- a significant improvement. Compare to 74S with similar consumption but a fraction of the delay (or 74F with several improvements, but that was Fairchild, not TI, so isn't quite a direct lineage).

So, a lot of tweaks won't be evident just from a DC analysis. Reduced supply consumption, sure, but how does that trade off with speed? If only DC mattered, we could use extremely small and weak transistors, and wait quite a long time for the logic operation to complete (perhaps ~µs?); and that is indeed practical for some applications, but not those that TTL was targeting, of course.

Note that, for modeling saturation, and Baker clamping, and general speed stuff, IC models are ideally needed. Board-level components have far too much capacitance (far larger junction size) than the parts on chip (there may also be process differences, like 7400's gold doping to reduce carrier lifetime; 74LS I think solved that with Baker clamping instead?). So don't expect to reproduce nearly the same performance. You can still observe the same performance improvements, of course; just don't expect a MMBT3904 to do better than 5ns or so. :)

As for schematics, Wikipedia shows a few:
https://upload.wikimedia.org/wikipedia/commons/a/ac/7400_Circuit.svg
https://upload.wikimedia.org/wikipedia/commons/8/85/74LS00_Circuit.svg
https://upload.wikimedia.org/wikipedia/commons/c/cc/Sch%C3%A9ma_DM74ALS00.png
[just adding the links to avoid clutter]

As you can see, the original simply used a pull-down resistor in this position. Curiously, this 74LS00 circuit shows a resistor, as well as a simplified input circuit and no Darlington, whereas the (older TI) datasheet shows a more developed circuit.

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So what is it doing? I said earlier it's a pull-down, but why?

Consider the transistor without resistors: it's a diode-strapped transistor. This would make a current mirror, where the ratio of emitter areas gives the ratio of input to output currents.

^{simulate this circuit – Schematic created using CircuitLab}

(Note CircuitLab doesn't provide complete models, so I've mimicked an area ratio by setting IS of one transistor 10 times higher, just for example.)

The bandwidth of a current mirror is alright, but it's not very efficient; and large area ratios necessarily have high capacitances -- one of the transistors has to be at least minimum feature size, and the other can only be larger. But for speed, likely all (except the outputs) should be minimum size.

With resistors, a bit more voltage drop is allowed, both by effectively raising Vbe, and by preventing collector current from rising further (it will eventually saturate, hence the schottky is still needed here).

^{simulate this circuit}

This basically isn't very different from the current mirror case, aside from the resistance reducing the current share (kind of like making a very small area transistor, despite the process limits I mentioned earlier). But the dynamics I think do a bit better than that.

Consider the behavior at turn-off. There is some charge stored in the transistor (albeit small -- again, it is Baker clamped!), so Ic stays up for a moment as Ib drops. Or, if nothing else, Vce is a Vf below Vbe, and will take a moment for its capacitance to charge up -- this charge pulls down on the output transistor's base just a little bit, turning it off faster than a resistor.

Further, notice how current drops to nearly zero at modest voltages. The base node won't fully discharge when current stops, at least not very quickly. This primes the node for conduction on a subsequent pulse. (This may be measurable as a difference in propagation delay, for relatively heavy pull-down loads, dependent on time between transitions. Or perhaps as variable falling-edge sharpness.)