Verilog: Self bitwise logical operation

Question

I want the output out variable to be the output of 4 input AND gates, and the input variable is input [3:0] in;

Is there any better option than doing it like this?

assign out = in[3] & in[2] & in[1] & in[0];

Is there any other way to do self bitwise operation? What if the vector size of input is large number of bits?

Answer 1

You can use the reduction-AND operator:

assign out = ∈

Refer to IEEE Std 1800-2017, section 11.4.9 Reduction operators.

The unary reduction operators shall perform a bitwise operation on a single operand to produce a single-bit result.

This scales to any number of bits in the input signal.