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Apart from physical observation, is there a way to know if my code will undergo a race condition?

For example, the following code has a race condition because both initial blocks will start at 0 simulation time in the active region, which is non-deterministic in nature:

module tb;
    reg a,b;

    initial $display("a=%0d | b=%0d", a, b);

    initial begin
        a = 1;
        b = 0;
        a <= b;
        b <= a;
    end
endmodule

But upon executing the code, I get an output - a=x | b=x, which doesn't indicate if it was a race condition.

toolic
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Killjoy
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1 Answers1

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I don't know of any Verilog simulators which can automatically identify and notify you of potential race conditions in the code, for example using messages in a log file. Also, Verilog does not have a built-in data type which would indicate a race. For example, reg can take on 1 of 4 values (01xz), but there is no way to know if the value was the result of a race.

Some Verilog code linting tools can notify you of potential race conditions, but that is typically restricted to the synthesizable subset of Verilog code (not including testbench code).

Some simulation waveform viewers have the capability to show zero-time glitches on signals which may indicate races. However, this is only useful if you happen to be looking at a particular signal during a specific time range. Again, it does not automatically give you a list of signals with races.

This means you need to rely on human code reviews to catch race conditions. Like everything, you learn good coding practices and write code which avoids bad situations like race conditions.

toolic
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