I’m using a 40 MHz TCXO to drive the clock input of an A/D chip. The output of the TCXO is DC coupled 1.8 V LVCMOS and it is specified in the TCXO datasheet that the output load is 10 pF // 10 kOhm. The clock input of the A/D should be AC coupled and shouldn’t exceed 1.5 V peak to peak (Pk-Pk). Moreover, the clock input of the A/D chip has a 10 pF capacitor in parallel with a 10 kOhm resistor (inside the chip).
As shown in the attached figure, I’m using a 39 pF capacitor (C1) to AC couple the output of the TCXO and to reduce the voltage swing across the A/D clock input to 1.43 V Pk-Pk. Please note that C2 and R1 are inside the A/D chip and I don’t have control over them.
I have the following question: using the attached figure, the impedance seen at the output of the TCXO is 7.959 pF // 10 KOhm while in the TCXO datasheet, it is mentioned that the output load is 10 pF // 10 KOhm. Is the circuit in the attached figure OK? Or Should I update it so that the impedance seen at the output of the TCXO is 10 pF // 10 KOhm while meeting the AC coupling and voltage swing requirements? Kindly advice.