How do I use conditional compilation in Xilinx Vivado?

Asked Jul 27 '23 at 17:55

Active Jul 27 '23 at 18:10

Viewed 38 times

I want to conditionally include one of three files if the respective macro for that file has been defined. Normally I would define the macros in a separate file, say defines.v, and then include that in the top module.

The top module file would look something like this:

`include "defines.v"

`ifdef CONDITION_1
`include "file1.v"

`elsif CONDITION_2
`include "file2.v"

`elsif CONDITION_3
`include "file3.v"
`endif

module top;
   ...
   ...
endmodule

and this would be the defines.v file:

`define CONDITION_1
// `define CONDITION_2
// `define CONDITION_3

To implement the same in Vivado, I added file1.v, file2.v, file3.v, defines.v along with the top module file in sources. But in this way, the top module includes all the other files present in sources automatically.

So I want to know what's the right way.

EDIT- By "added", I mean I added those files in the design sources folder:

edited Jul 27 '23 at 18:10

asked Jul 27 '23 at 17:55

Killjoy

what do you mean by _I added file1.v, file2.v_ ? The verilog code looks ok. You need to somehow show how you compiled all the code – toolic Jul 27 '23 at 18:04
@toolic Added in the design sources folder. Check my edit. – Killjoy Jul 27 '23 at 18:10
https://support.xilinx.com/s/article/54006?language=en_US – dave_59 Jul 27 '23 at 23:04

How do I use conditional compilation in Xilinx Vivado?

0 Answers0