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This question is from perspective of power integrity and not signal integrity. Power can be delivered from VRM to an IC using copper tracks and vias. Both of these have inductance and we want to minimize inductance. One to do this is to use decoupling capacitors and power planes. But in any case, from PDN PI perspective, what is worst, 1mm via or 1mm copper track?

Tracks and vias have different geometry. I am not sure if the same length of via and copper track have the same inductance. However, a geometry has affect on frequency response. This means that the signal attenuation will change for different frequency components. I am not sure if the response is worse for 1mm copper track or 1mm via.

quantum231
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In general, vias have a worse reputation than tracks. The current path necessarily rotates 90 degrees on entry and exit of the via, providing in each case a quarter of a turn which intuitively has more inductance than a straight track. More significant for power conductors though, while the track thickness is well-known (often 35 or 70um), the copper in the via itself is less easy to control and may be somewhat thinner, resulting in a higher DC voltage drop. That said, a 1mm hole has an effective track width of 3.14mm which may compensate. Anecdotally, I was working on a switch-mode circuit recently which unavoidably had a via in a critical location; I found that filling the via with solder improved the circuit’s efficiency by 2%.

Frog
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    Is 2% significant for SMPS? – gyuunyuu Aug 03 '23 at 11:20
  • In terms of power output it doesn’t matter much but when the power dissipated by the SMPS itself drops from 10 to 8% of input power then It’s quite significant – Frog Aug 03 '23 at 20:15