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TI manufacturers two near-identical drivers for matrixed LEDs, LP5890 and TLC6983. I was only able to determine the following differences:

Characteristic LP5890 [DataSheet] TLC6983 [DataSheet]
Applications • LED digital signage
• Keyboard, gaming accessories
• Major and smart home appliances
• Smart speaker, wired and wireless speaker
• Audio mixer, DJ equipment, and broadcast
• Access equipment, switches, and servers		 • Narrow Pixel Pitch (NPP) LED display
• Mini and micro-LED products
SCLK (external) 50 [MHz]
Rising Edge		 25 [MHz]
Dual Edge

Question

  • Are there tradeoffs between a rising-edge SCLK and its dual-edge, half-frequency equivalent?
  • Why might the dual-edge equivalent be recommended for the alternative application?
kando
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2 Answers2

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It's hard to tell what the manufacturer is getting at. No, I have not read the entire data sheet(s) yet. Maybe sometime soon.

But, our design guidelines have recommended against (can't say that it was prohibited) using both edges of the clock in general. One reason is that it's hard/impossible for the timing analysis tool to assess setup and hold time violations because they depend on the duty cycle of the clock. A design may pass and work OK with a rigidly constrained 50/50 duty clock, but may fail with a 60/40 duty cycle clock.

That said, there are devices that are designed specifically to work with both edges of a clock or some other signal. DDR memory is one. But in that case the timing parameters are tied down very tightly to guarantee proper operation.

SteveSh
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  • I see what you mean. My likely microcontroller ([`MSP430FR2676`](https://www.ti.com/product/MSP430FR2676)) lists its SCLK (Section 8.12.7 eUSCI) as f.cycle.max = 16 [MHz] and its duty as (50 ± 10) [%] — so dipping into 60/40 is entirely possible. – kando Jul 20 '23 at 13:00
  • The LED drivers do not *directly* specify duty limits. For SCLK: `TLC6983` : f.cycle.max = 25 [Mhz] --> T.cycle.min = 40 [ns]. T.high.min = T.low.min = 18 [ns]. Thus: T.high.min = T.low.min = 0.45 • T.cycle.min. Thus: D = (50 ± 5) [%]. `LP5890` : f.cycle.max = 50 [Mhz] --> T.cycle.min = 20 [ns]. T.high.min = T.low.min = 9 [ns]. (Again: D = (50 ± 5) [%].) If I used a f.cycle = 16 [MHz] --> T.cycle = 62.5 [ns] with duty = (50 ± 10) [%] --> T.high.min = T.low.min = 25 [ns]. I thus meet the LED driver criteria: f.cycle.max = 16 [Mhz] ≤ 25 [Mhz], T.high.min = T.low.min = 25 [ns] ≥ 9 [ns]. – kando Jul 20 '23 at 13:09
  • Duty tolerance max is thus calculated (not specified) to be 5% when considering T.cycle.min, T.high.min and T.low.min, but nothing is stated that T.high.min and T.low.min would change with T.cycle .. so when using a higher T.cycle (lower f.cycle), is it likely that T.high.min and T.low.min remain the same, or should D.tolerance.max have been specified? – kando Jul 20 '23 at 13:20
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Based on the applications listed, I'm assuming this signal is being sent down a cable of some sort.

Half the clock frequency is "easier" to drive. The cable capacitance will have less effect on the 25MHz signal compared to 50MHz. Potentially less radiated EMI at the lower frequency. A simpler/slower system can be used to drive the external clock.
Not every chip can drive an external pin that fast.

Aaron
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