Do all logic circuits have to have negligible input current?

Question

There are common configurations where, for example, a logical HIGH input (a voltage source) is connected to the input of some logic circuit through a resistor as shown there. Typically this logic circuit is represented as a diagram, without referring to a particular implementation of the logic gates.
I've never seen it specified that the gates are built in a way that we can assume no input current is drained into them. For the particular example it is a neccessary assumption, so that there is no voltage drop across the input resistor.

I undestand that most logic gates' inputs are directly connected to a base of a transistor and so drain no current, but is this a general requirement for a logic gate to be a logic gate?
Are there any logic gate implementations where input current indeed is significant?

Edit: indeed, I missed that in TTL logic the input is not connected to the base. Does this mean we cannot apply a logic input to it through a resistor?

Answer 1

No, there are different logic circuits with different implementations.

And even if the input would be a BJT transistor base, it would generally be an emitter follower with pull-up resistance on base.

While a CMOS input certainly draws almost no current, a TTL input does, and many other families that either have names or not, because any chip and pin, such as voltage regulator enable pin, can use any custom voltages and currents it defines in the data sheet. It may still be compatible with common logic outputs such as TTL or CMOS.

And we can have a resistor on input, as long as it has proper resistance for what it does. It depends on the logic family and what the circuit does, e.g. a simple case of pull-up resistor and pushbutton to ground on a MCU input.

For CMOS input, you could have a 100k resistor to VCC to keep input at VCC because no current flows in or out. Then pushbutton will connect to 0V when pushed. No problems there. You could also have a 100k pull-down and pushbutton to VCC, no difference. But you can't omit the resistor, as it would be an unconnected input, floating at any random voltage and receiving nearby electrical interference.

For TTL input, it's obviously more complex, because of the current flowing in or out. As long as the resistor keeps voltage at logic high at the input even if current flows, it's enough. The pushbutton will still apply 0V to input. The same is not true for pull-down. TTL input can source substantial amount of current when low, so a 100k pull-down would be useless. And because the internal structures would try to source current when pulling low, the internal structures also try to keep the input high even if there is no resistor, but one should not count on it.

Answer 2

A bipolar TTL logic input will source significant current when pulled Low.

Answer 3

Trivial case: you can make a logic circuit out of relays, which by their nature do not have negligible input current.

Answer 4

As well as the static current passed by some logic families, consider a simple inverter such as the SN74LVC1G04. In order to meet the maximum time for rise and fall (the datasheet is a bit misleading in the way they specify it) of 5ns/V with a 5V Vcc, assuming an input capacitance of 3pF you would need to source or sink a current of more than 0.6mA, which is not negligible- a resistor in the single digit KΩ would violate the limit (causing undesirable dissipation due to shoot-through currents). That's the slowest you're supposed to run the gates, not the optimal.

If you want to not degrade the ~2ns typical propagation delay much you'd need to supply more like 10mA-20mA for a short period of time, so more in the 100-200Ω range, very roughly.

Answer 5

Soviet chips frequently had the input current -1.6 mA for the logical zero (below 0.4 V) and 0.04 mA for the logical 1 (above 2.4 V), see the widespread К155ЛА3, the analog of SN7400 here for instance). This does really not look negligible. 2 mA is a common current to drive a miniature LED (source). Contra-intuitively, logical 0 was drawing more current ("pulling up"). A free-hanging input has been read as logical 1.

Answer 6

In general, all real implementations of electronic logic gates have an input current. Some very low, some quite high, some like a resistive load, some like a capacitive load, and anything in between or outside. There are many different techniques, old ones like DTL or TTL and newer ones like CMOS.

The linked example shows this schematic:

^{simulate this circuit – Schematic created using CircuitLab}

These resistors are used to provide the respective logic level, if the SPST switch is open. You cannot replace it with a direct wire, as it will short the source of the logic level, commonly ground or supply voltage, with the other side, when the switch is closed. Such a resistor limits the current when the switch is closed.

Anyway, your question is useful. What about the voltage drop because of the input current?

As we now know, there are different techniques. You need to know the input current to design the resistor in a way that the input accepts the voltage as the desired logic level. Techniques with a very low input current get away with bigger resistors, others with a very high input current need smaller resistors.

For example, a standard TTL low-power-Schottky input has these parameters:

\$V_{CC} = 4.75 V\$ (minimum)
\$V_{IH} = 2 V\$ (minimum)
\$V_{IL} = 0.8 V\$ (maximum)
\$I_{IH} = 20 µA\$ (maximum)
\$I_{IL} = -0.4 mA\$ (maximum)

Note: the negative sign on \$I_{IL}\$ designates that current as "sourcing" from the input.

For a working pull-down, the resistor needs to generate a voltage drop of maximum 0.8 V for the maximum input current of 0.4 mA. So it has to be less than or equal to:

\$R_{PDmax} = \frac{V_{max}}{I_{max}} = \frac{V_{IL}}{-I_{IL}} = \frac{0.8 V}{0.4 mA} = 2 k\Omega\$

The lower limit is given by the current specification of the switch and your desired current consumption.

Note: As we now see, the presented circuit will not work for a LS-TTL input.

For a working pull-up, the resistor needs to generate a voltage drop of maximum 2.75 V for the maximum input current of 20 µA. So it has to be less than or equal to:

\$R_{PUmax} = \frac{V_{max}}{I_{max}} = \frac{V_{CC} - V_{IH}}{I_{IH}} = \frac{4.75 V - 2 V}{0.02 mA} = 137.5 k\Omega\$

Again, the lower limit is given by the current specification of the switch and your desired current consumption.

A look in the linked data sheet reveals a pull-up at each input, nominally \$20 k\Omega\$. This is one reason why you can omit a pull-up resistor with such TTL inputs, and why the input current \$I_{IL}\$ is so much higher than \$I_{IH}\$.

With another technique, HCMOS for example in the 74HC04, the input current is maximum \$\pm1{\mu}A\$. The calculation for the resistors is left as an exercise to the reader.

This answer omits other properties that are some times important. For example, clock inputs need a maximum rise/fall time. You need to take the capacitance on the input wire into account, inductive effects, and so on, especially in high-speed applications.