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I traced a IO-Link USB master PCB to understand how it works. The ciruit I found makes sense to me except for a part of the programming interface. It's marked red in the following schematic. (TXDA is connected to a different IC, a CCE4510 IO-Link PHY.)

The TXD and RXD lines of the SCI programming interface (see Renesas RX231 manual chapter 49.8.2) are connected to other pins of the MCU via BRTs. I don't understand what the purpose of that could be.

enter image description here

The schematic might contain errors, though I'm fairly certain that part in red is correct. The biggest question mark is the dual BRT SUR502EF. The IC is in a SOT-563 package and has the marking "SS". There doesn't seem to be a pin 1 indicator. The only matching part I could find is the AUK SUR502EF dual digital transistor. The part seems to be obsolete though and not easily available while all other parts on the PCB seem to be easily available parts made by name brands. Here is a picture of the board:

enter image description here

Edit: A picture of the backside. The middle pins (2 & 5) of the part both have continuity to ground as shown in the schematic. enter image description here

nanash1
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  • Do you have a picture of the bottom side? NB, the absence of pin 1 mark is consistent with a symmetric twin transistor as you suggest. All the devices I've seen like this have bases on 2 and 5: are you certain about these being straight to gnd? – jonathanjo Jul 11 '23 at 13:11
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    @jonathanjo I have a picture of the bottom side, but I don't think it will be too helpful without overlaying it with the top side. There is a via under the part without a trace showing, so it's connected to an internal layer. I measured continuity to ground on both pins with a multimeter. As far as I can tell there are no signal traces on the inner layers, only a ground plane and power planes. – nanash1 Jul 11 '23 at 13:46

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The part marked SS is not a BRT as it turns out. It's actually a quad TVS diode array. Specifically it's a Semtech UCLAMP3304A.TCT.

enter image description here

(Source: lcsc.com)

This means the contacts on the back are just normal test connections. The updated schematic looks like this:

enter image description here

nanash1
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