Error while trying to bind SystemVerilog module with properties module

Question

I have a SystemVerilog module that I want to test using assertions. For simplicity let's say the DUT is this:

module dut (
    input logic [7:0] da
    output logic [7:0] db
);

    always_comb begin:
        if (da == '0)
            db <= '1;
        else
            db <= '0
    end
endmodule

I have also created a file containing a module with the assertions for the DUT:

module properties(
    input logic [7:0] pa,
    input logic [7:0] pb
);

    always_comb begin:
        assert final (pa == pb) $error("assertion failed"); else $display("PASS");
    end

endmodule

And finally I have a test bench:

module tb();

    logic [7:0] ta;
    logic [7:0] tb;

    dut dut_inst(.da(ta), .db(tb));

    bind dut_inst properties dut_bind(.pa(da), .pb(db));

    initial begin:

       // do something here...

    end

endmodule

The problem: When compiling the code I get two errors from Quartus :

The first one is about the properties module and says: Error (10170): Verilog HDL syntax error at properties.sv(6) near text: "final"; expecting "(". If I remove the final keyword the error goes away but I must use final to filter out simulation glitches.
The second one says Error (10170): Verilog HDL syntax error at tb.sv(8) near text: "bind"; expecting "endmodule".

What I have tried so far

Regarding the first issue I only tried to remove the final keyword but it is not a solution as I said before.

For the second error, I tried binding this way:

bind dut properties dut_bind(.pa(da), .pb(db));

but I get the same error. I also tried moving the bind out of the tb module like that:

module tb();

    logic [7:0] ta;
    logic [7:0] tb;

    dut dut_inst(.da(ta), .db(tb));

    initial begin:

       // do something here...

    end

endmodule

bind dut properties dut_bind(.pa(da), .pb(db));

but I got a similar error saying Error (10170): Verilog HDL syntax error at tb.sv(8) near text: "bind"; expecting a description. What am I doing wrong?

PS: I am using intel Quartus Prime lite edition.

What tool are you trying to use? Assertions are for simulation or formal checking tools, not synthesis. — dave_59, Jul 09 '23 at 01:32
@dave_59 I use modelsim for simulation and intel Quartus Prime lite edition for synthesis. I was under the impression that assertions where synthesisable — Kyriafinis Vasilis, Jul 09 '23 at 01:32
`syntax error at properties.sv(6) near text: "final";` is odd: Does line counting start at zero? — greybeard, Jul 09 '23 at 09:44
The error is coming from quartus and the syntax error is on the line `assert final (pa == pb)...` — Kyriafinis Vasilis, Jul 09 '23 at 10:33

Shashank V M · Accepted Answer · 2023-07-10T01:54:43.653

1

Bind syntax: bind dut : dut_inst properties dut_bind (.pa(da), .pb(db));

Place it inside the testbench module after instantiating the DUT.

Since Quartus tool is for synthesis, use a compiler directive to let the synthesis tool skip the assertion.

Example:

module tb();

    logic [7:0] ta;
    logic [7:0] tb;

    dut dut_inst(.da(ta), .db(tb));

// if SYNTHESIS is not defined, include below code  
`ifndef SYNTHESIS
    bind dut : dut_inst properties dut_bind (.pa(da), .pb(db));
`endif
// end if
    initial begin

       // do something here...

    end

endmodule

Pass SYNTHESIS as a compilation option during synthesis to let the tool skip the assertion.

edited Jul 10 '23 at 01:54

answered Jul 09 '23 at 08:06

Shashank V M

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What is and how do I use the directive you mentioned? – Kyriafinis Vasilis Jul 09 '23 at 10:35
@KyriafinisVasilis updated my answer – Shashank V M Jul 09 '23 at 10:40
@KyriafinisVasilis since Quartus is for synthesis, don't include testbench in it. Please accept my answer if that helped! – Shashank V M Jul 09 '23 at 10:55
1

I surrounded the bind with the `// synthesis translate_off` `// synthesis translate_on` directives and Quartus synthesized the code but now I have problems on modelsim saying `Error: (vsim-3033) Instantiation of 'properties' failed. The design unit was not found.`. I suspect it is because the design was not synthesized – Kyriafinis Vasilis Jul 09 '23 at 11:02
Also, I don't use the testbench as the top module and I have it set up in Quartus as a testbench for the dut – Kyriafinis Vasilis Jul 09 '23 at 11:05
So you got your Quartus synthesis working. The error from modelsim looks to me a separate question. Please ask it in a separate question. The current question is on Quartus Prime. – Shashank V M Jul 09 '23 at 11:08

Error while trying to bind SystemVerilog module with properties module

1 Answers1